diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index f0fd9140d..57ecb83ff 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -72,7 +72,7 @@ jobs: - uses: esp-rs/xtensa-toolchain@v1.5 with: ldproxy: false - version: 1.84.0.0 + version: 1.85.0.0 # Install the Rust stable toolchain for RISC-V devices: - uses: dtolnay/rust-toolchain@v1 with: diff --git a/.github/workflows/documentation.yml b/.github/workflows/documentation.yml index c7df66e36..aa04a7ab5 100644 --- a/.github/workflows/documentation.yml +++ b/.github/workflows/documentation.yml @@ -36,7 +36,7 @@ jobs: with: default: true ldproxy: false - version: 1.84.0.0 + version: 1.85.0.0 - name: Checkout repository uses: actions/checkout@v4 diff --git a/.github/workflows/hil.yml b/.github/workflows/hil.yml index bfb993750..39ffcb565 100644 --- a/.github/workflows/hil.yml +++ b/.github/workflows/hil.yml @@ -115,7 +115,7 @@ jobs: buildtargets: ${{ matrix.target.soc }} default: true ldproxy: false - version: 1.84.0.0 + version: 1.85.0.0 - name: Build tests run: cargo xtask build-tests ${{ matrix.target.soc }} diff --git a/esp-hal/src/interrupt/xtensa.rs b/esp-hal/src/interrupt/xtensa.rs index 27b02ae23..b8584ceaf 100644 --- a/esp-hal/src/interrupt/xtensa.rs +++ b/esp-hal/src/interrupt/xtensa.rs @@ -157,7 +157,7 @@ pub fn enable_direct(interrupt: Interrupt, cpu_interrupt: CpuInterrupt) -> Resul map(Cpu::current(), interrupt, cpu_interrupt); xtensa_lx::interrupt::enable_mask( - xtensa_lx::interrupt::get_mask() | 1 << cpu_interrupt as u32, + xtensa_lx::interrupt::get_mask() | (1 << cpu_interrupt as u32), ); } Ok(()) @@ -491,7 +491,7 @@ mod vectored { map(Cpu::current(), interrupt, cpu_interrupt); xtensa_lx::interrupt::enable_mask( - xtensa_lx::interrupt::get_mask() | 1 << cpu_interrupt as u32, + xtensa_lx::interrupt::get_mask() | (1 << cpu_interrupt as u32), ); } Ok(()) diff --git a/esp-hal/src/lcd_cam/lcd/i8080.rs b/esp-hal/src/lcd_cam/lcd/i8080.rs index af21afd0c..d904c66f3 100644 --- a/esp-hal/src/lcd_cam/lcd/i8080.rs +++ b/esp-hal/src/lcd_cam/lcd/i8080.rs @@ -343,7 +343,7 @@ where w.lcd_cmd().set_bit(); w.lcd_cmd_2_cycle_en().set_bit() }); - let cmd = first.into() as u32 | (second.into() as u32) << 16; + let cmd = first.into() as u32 | ((second.into() as u32) << 16); self.regs() .lcd_cmd_val() .write(|w| unsafe { w.lcd_cmd_value().bits(cmd) }); diff --git a/esp-hal/src/soc/esp32/efuse/mod.rs b/esp-hal/src/soc/esp32/efuse/mod.rs index 5066530f3..9b707b5ed 100644 --- a/esp-hal/src/soc/esp32/efuse/mod.rs +++ b/esp-hal/src/soc/esp32/efuse/mod.rs @@ -116,7 +116,7 @@ impl Efuse { /// Returns the CHIP_VER_PKG eFuse value. pub fn chip_type() -> ChipType { let chip_ver = Self::read_field_le::(CHIP_PACKAGE) - | Self::read_field_le::(CHIP_PACKAGE_4BIT) << 4; + | (Self::read_field_le::(CHIP_PACKAGE_4BIT) << 4); match chip_ver { 0 => ChipType::Esp32D0wdq6, diff --git a/esp-hal/src/soc/esp32/gpio.rs b/esp-hal/src/soc/esp32/gpio.rs index b6445c39e..2dc9765a3 100644 --- a/esp-hal/src/soc/esp32/gpio.rs +++ b/esp-hal/src/soc/esp32/gpio.rs @@ -115,7 +115,7 @@ pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { Cpu::AppCpu => int_enable as u8 | ((nmi_enable as u8) << 1), // this should be bits 3 & 4 respectively, according to the TRM, but it doesn't seem to // work. This does though. - Cpu::ProCpu => (int_enable as u8) << 2 | ((nmi_enable as u8) << 3), + Cpu::ProCpu => ((int_enable as u8) << 2) | ((nmi_enable as u8) << 3), } } diff --git a/esp-hal/src/soc/esp32/psram.rs b/esp-hal/src/soc/esp32/psram.rs index b0e61c40f..65c80b1d3 100644 --- a/esp-hal/src/soc/esp32/psram.rs +++ b/esp-hal/src/soc/esp32/psram.rs @@ -974,7 +974,7 @@ pub(crate) mod utils { // DPORT_SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14); DPORT::regs() .host_inf_sel() - .modify(|r, w| w.bits(r.bits() | 1 << 14)); + .modify(|r, w| w.bits(r.bits() | (1 << 14))); // Start send data spi.cmd().modify(|_, w| w.usr().set_bit()); diff --git a/esp-hal/src/soc/esp32s2/gpio.rs b/esp-hal/src/soc/esp32s2/gpio.rs index ce66bb28e..fc58f005f 100644 --- a/esp-hal/src/soc/esp32s2/gpio.rs +++ b/esp-hal/src/soc/esp32s2/gpio.rs @@ -121,7 +121,7 @@ pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static io_mux::GPIO0 { pub(crate) fn gpio_intr_enable(int_enable: bool, nmi_enable: bool) -> u8 { int_enable as u8 | ((nmi_enable as u8) << 1) - | (int_enable as u8) << 2 + | ((int_enable as u8) << 2) | ((nmi_enable as u8) << 3) } diff --git a/esp-hal/src/soc/esp32s2/psram.rs b/esp-hal/src/soc/esp32s2/psram.rs index aca734c7d..5e5c80b4a 100644 --- a/esp-hal/src/soc/esp32s2/psram.rs +++ b/esp-hal/src/soc/esp32s2/psram.rs @@ -238,7 +238,7 @@ pub(crate) mod utils { const PSRAM_EID_SIZE_M: u32 = 0x07; const PSRAM_EID_SIZE_S: u32 = 5; - let size_id = (((dev_id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S + let size_id = ((((dev_id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M; const PSRAM_EID_SIZE_32MBITS: u32 = 1; diff --git a/esp-hal/src/soc/esp32s2/trng.rs b/esp-hal/src/soc/esp32s2/trng.rs index 332fb7e3a..c85c667e1 100644 --- a/esp-hal/src/soc/esp32s2/trng.rs +++ b/esp-hal/src/soc/esp32s2/trng.rs @@ -287,7 +287,7 @@ pub(crate) fn regi2c_write_mask(block: u8, _host_id: u8, reg_add: u8, msb: u8, l // Read the i2c bus register let mut temp: u32 = ((block as u32 & I2C_RTC_SLAVE_ID_V as u32) << I2C_RTC_SLAVE_ID_S as u32) - | (reg_add as u32 & I2C_RTC_ADDR_V as u32) << I2C_RTC_ADDR_S as u32; + | ((reg_add as u32 & I2C_RTC_ADDR_V as u32) << I2C_RTC_ADDR_S as u32); reg_write(I2C_RTC_CONFIG2, temp); while reg_get_bit(I2C_RTC_CONFIG2, I2C_RTC_BUSY) != 0 {} temp = reg_get_field(I2C_RTC_CONFIG2, I2C_RTC_DATA_S, I2C_RTC_DATA_V); diff --git a/esp-hal/src/soc/esp32s3/psram.rs b/esp-hal/src/soc/esp32s3/psram.rs index a194112ee..727fe2d82 100644 --- a/esp-hal/src/soc/esp32s3/psram.rs +++ b/esp-hal/src/soc/esp32s3/psram.rs @@ -274,7 +274,7 @@ pub(crate) mod utils { const PSRAM_EID_SIZE_M: u32 = 0x07; const PSRAM_EID_SIZE_S: u32 = 5; - let size_id = (((dev_id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S + let size_id = ((((dev_id) >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S) & PSRAM_EID_SIZE_M; const PSRAM_EID_SIZE_32MBITS: u32 = 1; diff --git a/esp-hal/src/system.rs b/esp-hal/src/system.rs index 6000ce60e..f8ce156ba 100755 --- a/esp-hal/src/system.rs +++ b/esp-hal/src/system.rs @@ -445,7 +445,7 @@ impl PeripheralClockControl { } #[cfg(all(rsa, esp32))] Peripheral::Rsa => { - peri_clk_en.modify(|r, w| unsafe { w.bits(r.bits() | (enable as u32) << 2) }); + peri_clk_en.modify(|r, w| unsafe { w.bits(r.bits() | ((enable as u32) << 2)) }); } #[cfg(all(rsa, any(esp32c3, esp32s2, esp32s3)))] Peripheral::Rsa => { @@ -658,7 +658,7 @@ impl PeripheralClockControl { } #[cfg(all(rsa, esp32))] Peripheral::Rsa => { - peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() | 1 << 2) }); + peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() | (1 << 2)) }); peri_rst_en.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << 2)) }); } #[cfg(all(rsa, any(esp32c3, esp32s2, esp32s3)))] diff --git a/esp-hal/src/time.rs b/esp-hal/src/time.rs index c2221d574..22c8c394b 100644 --- a/esp-hal/src/time.rs +++ b/esp-hal/src/time.rs @@ -442,7 +442,7 @@ fn now() -> Instant { }; let hi = tg0.lacthi().read().bits(); - let ticks = (hi as u64) << 32u64 | lo as u64; + let ticks = ((hi as u64) << 32u64) | lo as u64; (ticks, 16) }; diff --git a/esp-hal/src/touch.rs b/esp-hal/src/touch.rs index e4c83cd49..103f5ba8a 100644 --- a/esp-hal/src/touch.rs +++ b/esp-hal/src/touch.rs @@ -468,7 +468,7 @@ fn internal_enable_interrupt(touch_nr: u8) { SENS::regs().sar_touch_enable().modify(|r, w| unsafe { w.touch_pad_outen1() - .bits(r.touch_pad_outen1().bits() | 1 << touch_nr) + .bits(r.touch_pad_outen1().bits() | (1 << touch_nr)) }); } diff --git a/esp-storage/src/esp32.rs b/esp-storage/src/esp32.rs index 85956aca3..d17c737cc 100644 --- a/esp-storage/src/esp32.rs +++ b/esp-storage/src/esp32.rs @@ -145,7 +145,7 @@ pub(crate) fn spiflash_write(dest_addr: u32, data: *const u32, len: u32) -> i32 let block_len = if len - block < 32 { len - block } else { 32 }; write_register( SPI_ADDR_REG, - ((dest_addr + block) & 0xffffff) | block_len << 24, + ((dest_addr + block) & 0xffffff) | (block_len << 24), ); let data_ptr = unsafe { data.offset((block / 4) as isize) }; @@ -215,7 +215,7 @@ fn spiflash_wait_for_ready() { #[link_section = ".rwtext"] pub(crate) fn spiflash_unlock() -> i32 { let flashchip = FLASH_CHIP_ADDR as *const EspRomSpiflashChipT; - if unsafe { (*flashchip).device_id } >> 16 & 0xff == 0x9D { + if (unsafe { (*flashchip).device_id } >> 16) & 0xff == 0x9D { panic!("ISSI flash is not supported"); } diff --git a/esp-wifi/src/preempt_builtin/preempt_xtensa.rs b/esp-wifi/src/preempt_builtin/preempt_xtensa.rs index 51cd9bd28..4412f7b37 100644 --- a/esp-wifi/src/preempt_builtin/preempt_xtensa.rs +++ b/esp-wifi/src/preempt_builtin/preempt_xtensa.rs @@ -42,7 +42,7 @@ pub(crate) fn task_create( let stack_ptr = task_stack_ptr - (task_stack_ptr % 16); (*ctx).trap_frame.A1 = stack_ptr as u32; - (*ctx).trap_frame.PS = 0x00040000 | (1 & 3) << 16; // For windowed ABI set WOE and CALLINC (pretend task was 'call4'd). + (*ctx).trap_frame.PS = 0x00040000 | ((1 & 3) << 16); // For windowed ABI set WOE and CALLINC (pretend task was 'call4'd). (*ctx).trap_frame.A0 = 0; diff --git a/esp-wifi/src/preempt_builtin/timer/xtensa.rs b/esp-wifi/src/preempt_builtin/timer/xtensa.rs index 123b31503..7c59137a7 100644 --- a/esp-wifi/src/preempt_builtin/timer/xtensa.rs +++ b/esp-wifi/src/preempt_builtin/timer/xtensa.rs @@ -35,9 +35,10 @@ pub(crate) fn setup_multitasking() { unsafe { let enabled = xtensa_lx::interrupt::disable(); xtensa_lx::interrupt::enable_mask( - 1 << 29 // Software1 + (1 << 29) | xtensa_lx_rt::interrupt::CpuInterruptLevel::Level2.mask() - | xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask() | enabled, + | xtensa_lx_rt::interrupt::CpuInterruptLevel::Level6.mask() + | enabled, ); } }