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Fix new clippy lint (#1581)

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* Fix new clippy lint

* All the RISCVs
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Dominic Fischer 2024-05-23 14:25:34 +01:00 committed by GitHub
parent cc28c3eb09
commit bd4b044748
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1
esp-hal/src/soc/esp32c2/gpio.rs
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@ -36,6 +36,7 @@
//! two different banks: //! two different banks:
//! * `InterruptStatusRegisterAccessBank0` //! * `InterruptStatusRegisterAccessBank0`
//! * `InterruptStatusRegisterAccessBank1`. //! * `InterruptStatusRegisterAccessBank1`.
//!
//! This trait provides functions to read the interrupt status and NMI status //! This trait provides functions to read the interrupt status and NMI status
//! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
//! `gpio` peripheral to access the appropriate registers. //! `gpio` peripheral to access the appropriate registers.

1
esp-hal/src/soc/esp32c3/gpio.rs
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@ -36,6 +36,7 @@
//! two different banks: //! two different banks:
//! * `InterruptStatusRegisterAccessBank0` //! * `InterruptStatusRegisterAccessBank0`
//! * `InterruptStatusRegisterAccessBank1`. //! * `InterruptStatusRegisterAccessBank1`.
//!
//! This trait provides functions to read the interrupt status and NMI status //! This trait provides functions to read the interrupt status and NMI status
//! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
//! `gpio` peripheral to access the appropriate registers. //! `gpio` peripheral to access the appropriate registers.

1
esp-hal/src/soc/esp32c6/gpio.rs
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@ -36,6 +36,7 @@
//! two different banks: //! two different banks:
//! * `InterruptStatusRegisterAccessBank0` //! * `InterruptStatusRegisterAccessBank0`
//! * `InterruptStatusRegisterAccessBank1`. //! * `InterruptStatusRegisterAccessBank1`.
//!
//! This trait provides functions to read the interrupt status and NMI status //! This trait provides functions to read the interrupt status and NMI status
//! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
//! `gpio` peripheral to access the appropriate registers. //! `gpio` peripheral to access the appropriate registers.

1
esp-hal/src/soc/esp32h2/gpio.rs
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@ -36,6 +36,7 @@
//! two different banks: //! two different banks:
//! * `InterruptStatusRegisterAccessBank0` //! * `InterruptStatusRegisterAccessBank0`
//! * `InterruptStatusRegisterAccessBank1`. //! * `InterruptStatusRegisterAccessBank1`.
//!
//! This trait provides functions to read the interrupt status and NMI status //! This trait provides functions to read the interrupt status and NMI status
//! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the //! registers for both the `PRO CPU` and `APP CPU`. The implementation uses the
//! `gpio` peripheral to access the appropriate registers. //! `gpio` peripheral to access the appropriate registers.