mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-02 14:44:42 +00:00
Add DMA support for ESP32-S3
This commit is contained in:
Jesse Braham
parent
e2df98da52
commit
c642c79297
@ -5,7 +5,7 @@ use crate::{
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system::{Peripheral, PeripheralClockControl},
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};
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macro_rules! ImplChannel {
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macro_rules! impl_channel {
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($num: literal) => {
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paste::paste! {
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pub struct [<Channel $num>] {}
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@ -18,23 +18,37 @@ macro_rules! ImplChannel {
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fn set_out_burstmode(burst_mode: bool) {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<out_conf0_ch $num>].modify(|_,w| {
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w.[<out_data_burst_en_ch $num>]().bit(burst_mode)
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.[<outdscr_burst_en_ch $num>]().bit(burst_mode)
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});
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#[cfg(esp32s3)]
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dma.[<out_conf0_ch $num>].modify(|_,w| {
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w.out_data_burst_en_ch().bit(burst_mode)
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.outdscr_burst_en_ch().bit(burst_mode)
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});
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}
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fn set_out_priority(priority: DmaPriority) {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<out_pri_ch $num>].write(|w| {
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w.[<tx_pri_ch $num>]().variant(priority as u8)
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});
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#[cfg(esp32s3)]
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dma.[<out_pri_ch $num>].write(|w| {
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w.tx_pri_ch().variant(priority as u8)
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});
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}
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fn clear_out_interrupts() {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<int_clr_ch $num>].write(|w| {
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w.[<out_eof_ch $num _int_clr>]()
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.set_bit()
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@ -49,62 +63,132 @@ macro_rules! ImplChannel {
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.[<outfifo_udf_ch $num _int_clr>]()
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.set_bit()
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});
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#[cfg(esp32s3)]
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dma.[<out_int_clr_ch $num>].write(|w| {
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w.out_eof_ch_int_clr()
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.set_bit()
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.out_dscr_err_ch_int_clr()
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.set_bit()
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.out_done_ch_int_clr()
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.set_bit()
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.out_total_eof_ch_int_clr()
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.set_bit()
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.outfifo_ovf_l1_ch_int_clr()
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.set_bit()
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.outfifo_ovf_l3_ch_int_clr()
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.set_bit()
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.outfifo_udf_l1_ch_int_clr()
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.set_bit()
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.outfifo_udf_l3_ch_int_clr()
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.set_bit()
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});
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}
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fn reset_out() {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<out_conf0_ch $num>].modify(|_, w| w.[<out_rst_ch $num>]().set_bit());
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#[cfg(not(esp32s3))]
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dma.[<out_conf0_ch $num>].modify(|_, w| w.[<out_rst_ch $num>]().clear_bit());
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#[cfg(esp32s3)]
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dma.[<out_conf0_ch $num>].modify(|_, w| w.out_rst_ch().set_bit());
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#[cfg(esp32s3)]
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dma.[<out_conf0_ch $num>].modify(|_, w| w.out_rst_ch().clear_bit());
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}
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fn set_out_descriptors(address: u32) {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<out_link_ch $num>]
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.modify(|_, w| unsafe { w.[<outlink_addr_ch $num>]().bits(address) });
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#[cfg(esp32s3)]
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dma.[<out_link_ch $num>].modify(|_, w| unsafe { w.outlink_addr_ch().bits(address) });
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}
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fn has_out_descriptor_error() -> bool {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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dma.[<int_raw_ch $num>].read().[<out_dscr_err_ch $num _int_raw>]().bit()
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#[cfg(esp32s3)]
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let ret = dma.[<out_int_raw_ch $num>].read().out_dscr_err_ch_int_raw().bit();
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#[cfg(not(esp32s3))]
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let ret = dma.[<int_raw_ch $num>].read().[<out_dscr_err_ch $num _int_raw>]().bit();
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ret
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}
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fn set_out_peripheral(peripheral: u8) {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<out_peri_sel_ch $num>]
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.modify(|_, w| w.[<peri_out_sel_ch $num>]().variant(peripheral));
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#[cfg(esp32s3)]
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dma.[<out_peri_sel_ch $num>].modify(|_, w| w.peri_out_sel_ch().variant(peripheral));
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}
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fn start_out() {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<out_link_ch $num>]
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.modify(|_, w| w.[<outlink_start_ch $num>]().set_bit());
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#[cfg(esp32s3)]
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dma.[<out_link_ch $num>].modify(|_, w| w.outlink_start_ch().set_bit());
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}
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fn is_out_done() -> bool {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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dma.[<int_raw_ch $num>].read().[<out_total_eof_ch $num _int_raw>]().bit()
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#[cfg(not(esp32s3))]
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let ret = dma.[<int_raw_ch $num>].read().[<out_total_eof_ch $num _int_raw>]().bit();
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#[cfg(esp32s3)]
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let ret = dma.[<out_int_raw_ch $num>].read().out_total_eof_ch_int_raw().bit();
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ret
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}
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fn set_in_burstmode(burst_mode: bool) {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<in_conf0_ch $num>].modify(|_,w| {
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w.[<in_data_burst_en_ch $num>]().bit(burst_mode)
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.[<indscr_burst_en_ch $num>]().bit(burst_mode)
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});
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#[cfg(esp32s3)]
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dma.[<in_conf0_ch $num>].modify(|_,w| {
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w.in_data_burst_en_ch().bit(burst_mode).indscr_burst_en_ch().bit(burst_mode)
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});
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}
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fn set_in_priority(priority: DmaPriority) {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<in_pri_ch $num>].write(|w| {
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w.[<rx_pri_ch $num>]().variant(priority as u8)
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});
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#[cfg(esp32s3)]
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dma.[<in_pri_ch $num>].write(|w| {
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w.rx_pri_ch().variant(priority as u8)
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});
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}
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fn clear_in_interrupts() {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<int_clr_ch $num>].write(|w| {
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w.[<in_suc_eof_ch $num _int_clr>]()
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.set_bit()
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@ -121,40 +205,99 @@ macro_rules! ImplChannel {
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.[<infifo_udf_ch $num _int_clr>]()
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.set_bit()
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});
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#[cfg(esp32s3)]
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dma.[<in_int_clr_ch $num>].write(|w| {
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w.in_suc_eof_ch_int_clr()
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.set_bit()
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.in_err_eof_ch_int_clr()
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.set_bit()
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.in_dscr_err_ch_int_clr()
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.set_bit()
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.in_dscr_empty_ch_int_clr()
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.set_bit()
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.in_done_ch_int_clr()
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.set_bit()
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.infifo_ovf_l1_ch_int_clr()
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.set_bit()
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.infifo_ovf_l3_ch_int_clr()
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.set_bit()
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.infifo_udf_l1_ch_int_clr()
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.set_bit()
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.infifo_udf_l3_ch_int_clr()
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.set_bit()
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});
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}
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fn reset_in() {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<in_conf0_ch $num>].modify(|_, w| w.[<in_rst_ch $num>]().set_bit());
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#[cfg(not(esp32s3))]
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dma.[<in_conf0_ch $num>].modify(|_, w| w.[<in_rst_ch $num>]().clear_bit());
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#[cfg(esp32s3)]
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dma.[<in_conf0_ch $num>].modify(|_, w| w.in_rst_ch().set_bit());
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#[cfg(esp32s3)]
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dma.[<in_conf0_ch $num>].modify(|_, w| w.in_rst_ch().clear_bit());
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}
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fn set_in_descriptors(address: u32) {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<in_link_ch $num>]
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.modify(|_, w| unsafe { w.[<inlink_addr_ch $num>]().bits(address) });
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#[cfg(esp32s3)]
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dma.[<in_link_ch $num>].modify(|_, w| unsafe { w.inlink_addr_ch().bits(address) });
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}
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fn has_in_descriptor_error() -> bool {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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dma.[<int_raw_ch $num>].read().[<in_dscr_err_ch $num _int_raw>]().bit()
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#[cfg(not(esp32s3))]
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let ret = dma.[<int_raw_ch $num>].read().[<in_dscr_err_ch $num _int_raw>]().bit();
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#[cfg(esp32s3)]
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let ret = dma.[<in_int_raw_ch $num>].read().in_dscr_err_ch_int_raw().bit();
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ret
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}
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fn set_in_peripheral(peripheral: u8) {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<in_peri_sel_ch $num>]
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.modify(|_, w| w.[<peri_in_sel_ch $num>]().variant(peripheral));
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#[cfg(esp32s3)]
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dma.[<in_peri_sel_ch $num>].modify(|_, w| w.peri_in_sel_ch().variant(peripheral));
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}
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fn start_in() {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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#[cfg(not(esp32s3))]
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dma.[<in_link_ch $num>]
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.modify(|_, w| w.[<inlink_start_ch $num>]().set_bit());
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#[cfg(esp32s3)]
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dma.[<in_link_ch $num>].modify(|_, w| w.inlink_start_ch().set_bit());
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}
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fn is_in_done() -> bool {
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let dma = unsafe { &*crate::pac::DMA::PTR };
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dma.[<int_raw_ch $num>].read().[<in_suc_eof_ch $num _int_raw>]().bit()
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#[cfg(not(esp32s3))]
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let ret = dma.[<int_raw_ch $num>].read().[<in_suc_eof_ch $num _int_raw>]().bit();
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#[cfg(esp32s3)]
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let ret = dma.[<in_int_raw_ch $num>].read().in_suc_eof_ch_int_raw().bit();
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ret
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}
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}
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@ -166,8 +309,7 @@ macro_rules! ImplChannel {
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impl<'a> RxChannel<[<Channel $num>]> for [<Channel $num RxImpl>] {}
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pub struct [<ChannelCreator $num>] {
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}
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pub struct [<ChannelCreator $num>] {}
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impl [<ChannelCreator $num>] {
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pub fn configure<'a>(
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@ -219,11 +361,11 @@ macro_rules! ImplChannel {
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pub(crate) mod private {
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use crate::dma::{private::*, *};
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ImplChannel!(0);
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impl_channel!(0);
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#[cfg(not(esp32c2))]
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ImplChannel!(1);
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impl_channel!(1);
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#[cfg(not(esp32c2))]
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ImplChannel!(2);
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impl_channel!(2);
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}
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/// GDMA Peripheral
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@ -4,7 +4,7 @@ use core::{marker::PhantomData, sync::atomic::compiler_fence};
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use private::*;
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#[cfg(any(esp32c2, esp32c3))]
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#[cfg(any(esp32c2, esp32c3, esp32s3))]
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pub mod gdma;
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#[cfg(any(esp32, esp32s2))]
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@ -80,6 +80,23 @@ pub enum DmaPeripheral {
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Spi3 = 1,
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}
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/// DMA capable peripherals
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/// The values need to match the TRM
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#[cfg(esp32s3)]
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#[derive(Clone, Copy)]
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pub enum DmaPeripheral {
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Spi2 = 0,
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Spi3 = 1,
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Uhci0 = 2,
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I2s0 = 3,
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I2s1 = 4,
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LcdCam = 5,
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Aes = 6,
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Sha = 7,
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Adc = 8,
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Rmt = 9,
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}
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enum Owner {
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Cpu = 0,
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Dma = 1,
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@ -186,7 +203,7 @@ pub(crate) mod private {
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pub trait Spi2Peripheral: SpiPeripheral + PeripheralMarker {}
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/// Marks channels as useable for SPI3
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#[cfg(any(esp32, esp32s2))]
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#[cfg(any(esp32, esp32s2, esp32s3))]
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pub trait Spi3Peripheral: SpiPeripheral + PeripheralMarker {}
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/// DMA Rx
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@ -51,7 +51,6 @@ pub use self::{
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pub mod analog;
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pub mod clock;
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pub mod delay;
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#[cfg(any(esp32, esp32c2, esp32c3, esp32s2))]
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pub mod dma;
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pub mod gpio;
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pub mod i2c;
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@ -50,14 +50,13 @@
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use fugit::HertzU32;
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#[cfg(any(esp32, esp32c2, esp32c3, esp32s2))]
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use crate::dma::{
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private::{Rx, Tx},
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DmaError,
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DmaPeripheral,
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};
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use crate::{
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clock::Clocks,
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dma::{
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private::{Rx, Tx},
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DmaError,
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DmaPeripheral,
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},
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pac::spi2::RegisterBlock,
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system::PeripheralClockControl,
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types::{InputSignal, OutputSignal},
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@ -78,13 +77,11 @@ const MAX_DMA_SIZE: usize = 32736;
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#[derive(Debug, Clone, Copy)]
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pub enum Error {
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#[cfg(any(esp32, esp32c2, esp32c3, esp32s2))]
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DmaError(DmaError),
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MaxDmaTransferSizeExceeded,
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Unknown,
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}
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#[cfg(any(esp32, esp32c2, esp32c3, esp32s2))]
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impl From<DmaError> for Error {
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fn from(value: DmaError) -> Self {
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Error::DmaError(value)
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@ -264,7 +261,6 @@ where
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}
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}
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#[cfg(any(esp32, esp32c2, esp32c3, esp32s2))]
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pub mod dma {
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use core::mem;
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@ -918,7 +914,6 @@ mod ehal1 {
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}
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}
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#[cfg(any(esp32, esp32c2, esp32c3, esp32s2))]
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pub trait InstanceDma<TX, RX>: Instance
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where
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TX: Tx,
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@ -1073,7 +1068,7 @@ where
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}
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}
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#[cfg(any(esp32c2, esp32c3))]
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#[cfg(any(esp32c2, esp32c3, esp32s3))]
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fn enable_dma(&self) {
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let reg_block = self.register_block();
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reg_block.dma_conf.modify(|_, w| w.dma_tx_ena().set_bit());
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@ -1085,7 +1080,7 @@ where
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// for non GDMA this is done in `assign_tx_device` / `assign_rx_device`
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}
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#[cfg(any(esp32c2, esp32c3))]
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#[cfg(any(esp32c2, esp32c3, esp32s3))]
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fn clear_dma_interrupts(&self) {
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let reg_block = self.register_block();
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reg_block.dma_int_clr.write(|w| {
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@ -1128,7 +1123,6 @@ where
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}
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}
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#[cfg(any(esp32, esp32c2, esp32c3, esp32s2))]
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||||
impl<TX, RX> InstanceDma<TX, RX> for crate::pac::SPI2
|
||||
where
|
||||
TX: Tx,
|
||||
@ -1136,7 +1130,7 @@ where
|
||||
{
|
||||
}
|
||||
|
||||
#[cfg(any(esp32, esp32s2))]
|
||||
#[cfg(any(esp32, esp32s2, esp32s3))]
|
||||
impl<TX, RX> InstanceDma<TX, RX> for crate::pac::SPI3
|
||||
where
|
||||
TX: Tx,
|
||||
@ -1708,10 +1702,10 @@ impl Instance for crate::pac::SPI3 {
|
||||
|
||||
pub trait Spi2Instance {}
|
||||
|
||||
#[cfg(any(esp32, esp32s2))]
|
||||
#[cfg(any(esp32, esp32s2, esp32s3))]
|
||||
pub trait Spi3Instance {}
|
||||
|
||||
impl Spi2Instance for crate::pac::SPI2 {}
|
||||
|
||||
#[cfg(any(esp32, esp32s2))]
|
||||
#[cfg(any(esp32, esp32s2, esp32s3))]
|
||||
impl Spi3Instance for crate::pac::SPI3 {}
|
||||
|
||||
@ -26,7 +26,7 @@ pub enum Peripheral {
|
||||
Ledc,
|
||||
#[cfg(any(esp32c2, esp32c3))]
|
||||
ApbSarAdc,
|
||||
#[cfg(any(esp32c2, esp32c3))]
|
||||
#[cfg(any(esp32c2, esp32c3, esp32s3))]
|
||||
Gdma,
|
||||
#[cfg(any(esp32, esp32s2))]
|
||||
Dma,
|
||||
@ -47,7 +47,7 @@ impl PeripheralClockControl {
|
||||
#[cfg(esp32)]
|
||||
let (perip_clk_en0, perip_rst_en0) = { (&system.perip_clk_en, &system.perip_rst_en) };
|
||||
|
||||
#[cfg(any(esp32c2, esp32c3))]
|
||||
#[cfg(any(esp32c2, esp32c3, esp32s3))]
|
||||
let (perip_clk_en1, perip_rst_en1) = { (&system.perip_clk_en1, &system.perip_rst_en1) };
|
||||
|
||||
match peripheral {
|
||||
@ -89,7 +89,7 @@ impl PeripheralClockControl {
|
||||
perip_clk_en0.modify(|_, w| w.apb_saradc_clk_en().set_bit());
|
||||
perip_rst_en0.modify(|_, w| w.apb_saradc_rst().clear_bit());
|
||||
}
|
||||
#[cfg(any(any(esp32c2, esp32c3)))]
|
||||
#[cfg(any(any(esp32c2, esp32c3, esp32s3)))]
|
||||
Peripheral::Gdma => {
|
||||
perip_clk_en1.modify(|_, w| w.dma_clk_en().set_bit());
|
||||
perip_rst_en1.modify(|_, w| w.dma_rst().clear_bit());
|
||||
|
||||
123
esp32s3-hal/examples/spi_loopback_dma.rs
Normal file
123
esp32s3-hal/examples/spi_loopback_dma.rs
Normal file
@ -0,0 +1,123 @@
|
||||
//! SPI loopback test using DMA
|
||||
//!
|
||||
//! Folowing pins are used:
|
||||
//! SCLK GPIO6
|
||||
//! MISO GPIO2
|
||||
//! MOSI GPIO7
|
||||
//! CS GPIO10
|
||||
//!
|
||||
//! Depending on your target and the board you are using you have to change the
|
||||
//! pins.
|
||||
//!
|
||||
//! This example transfers data via SPI.
|
||||
//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
|
||||
//! data.
|
||||
|
||||
#![no_std]
|
||||
#![no_main]
|
||||
|
||||
use esp32s3_hal::{
|
||||
clock::ClockControl,
|
||||
dma::{DmaPriority, DmaTransferRxTx},
|
||||
gdma::Gdma,
|
||||
gpio::IO,
|
||||
pac::Peripherals,
|
||||
prelude::*,
|
||||
spi::{dma::WithDmaSpi2, Spi, SpiMode},
|
||||
timer::TimerGroup,
|
||||
Delay,
|
||||
Rtc,
|
||||
};
|
||||
use esp_backtrace as _;
|
||||
use esp_println::println;
|
||||
use xtensa_lx_rt::entry;
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
let peripherals = Peripherals::take().unwrap();
|
||||
let mut system = peripherals.SYSTEM.split();
|
||||
let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
|
||||
|
||||
// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
|
||||
// the RTC WDT, and the TIMG WDTs.
|
||||
let mut rtc = Rtc::new(peripherals.RTC_CNTL);
|
||||
let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
|
||||
let mut wdt0 = timer_group0.wdt;
|
||||
let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
|
||||
let mut wdt1 = timer_group1.wdt;
|
||||
|
||||
rtc.swd.disable();
|
||||
rtc.rwdt.disable();
|
||||
wdt0.disable();
|
||||
wdt1.disable();
|
||||
|
||||
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
|
||||
let sclk = io.pins.gpio6;
|
||||
let miso = io.pins.gpio2;
|
||||
let mosi = io.pins.gpio7;
|
||||
let cs = io.pins.gpio10;
|
||||
|
||||
let dma = Gdma::new(peripherals.DMA, &mut system.peripheral_clock_control);
|
||||
let dma_channel = dma.channel0;
|
||||
|
||||
let mut descriptors = [0u32; 8 * 3];
|
||||
let mut rx_descriptors = [0u32; 8 * 3];
|
||||
|
||||
let mut spi = Spi::new(
|
||||
peripherals.SPI2,
|
||||
sclk,
|
||||
mosi,
|
||||
miso,
|
||||
cs,
|
||||
100u32.kHz(),
|
||||
SpiMode::Mode0,
|
||||
&mut system.peripheral_clock_control,
|
||||
&clocks,
|
||||
)
|
||||
.with_dma(dma_channel.configure(
|
||||
false,
|
||||
&mut descriptors,
|
||||
&mut rx_descriptors,
|
||||
DmaPriority::Priority0,
|
||||
));
|
||||
|
||||
let mut delay = Delay::new(&clocks);
|
||||
|
||||
// DMA buffer require a static life-time
|
||||
let mut send = buffer1();
|
||||
let mut receive = buffer2();
|
||||
let mut i = 0;
|
||||
|
||||
for (i, v) in send.iter_mut().enumerate() {
|
||||
*v = (i % 255) as u8;
|
||||
}
|
||||
|
||||
loop {
|
||||
send[0] = i;
|
||||
send[send.len() - 1] = i;
|
||||
i = i.wrapping_add(1);
|
||||
|
||||
let transfer = spi.dma_transfer(send, receive).unwrap();
|
||||
// here we could do something else while DMA transfer is in progress
|
||||
// the buffers and spi is moved into the transfer and we can get it back via
|
||||
// `wait`
|
||||
(receive, send, spi) = transfer.wait();
|
||||
println!(
|
||||
"{:x?} .. {:x?}",
|
||||
&receive[..10],
|
||||
&receive[receive.len() - 10..]
|
||||
);
|
||||
|
||||
delay.delay_ms(250u32);
|
||||
}
|
||||
}
|
||||
|
||||
fn buffer1() -> &'static mut [u8; 32000] {
|
||||
static mut BUFFER: [u8; 32000] = [0u8; 32000];
|
||||
unsafe { &mut BUFFER }
|
||||
}
|
||||
|
||||
fn buffer2() -> &'static mut [u8; 32000] {
|
||||
static mut BUFFER: [u8; 32000] = [0u8; 32000];
|
||||
unsafe { &mut BUFFER }
|
||||
}
|
||||
@ -6,6 +6,7 @@ pub use embedded_hal as ehal;
|
||||
pub use esp_hal_common::{
|
||||
clock,
|
||||
cpu_control::CpuControl,
|
||||
dma::{self, gdma},
|
||||
efuse,
|
||||
gpio as gpio_types,
|
||||
i2c,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user