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Rename ESP_HAL_CONFIG_PLACE_SPI_MASTER_DRIVER_IN_RAM (#3402)

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Co-authored-by: Scott Mabin <scott@mabez.dev>
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Dániel Buga 2025-04-22 11:09:07 +02:00 committed by GitHub
parent d5f8f297ab
commit df6aa9c18f
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4 changed files with 38 additions and 27 deletions
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1
esp-hal/CHANGELOG.md
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@ -40,6 +40,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Moved DMA channel types from `esp_hal::dma::DmaChannelN`/`esp_hal::dma::XYDmaChannel` to `esp_hal::peripherals::DMA_XY` (#3372)
- `ParlIoFullDuplex`, `ParlIoTxOnly` and `ParlIoRxOnly` have been merged into `ParlIo` (#3366)
- All `Camera` pins are now configured using `with_*()` methods (#3237)
- The `ESP_HAL_CONFIG_PLACE_SPI_DRIVER_IN_RAM` configuration option has been renamed to `ESP_HAL_CONFIG_PLACE_SPI_MASTER_DRIVER_IN_RAM`. (#3402)
- Made the `ParlIo` traits for `TxPins`, `RxPins`, `ConfigurePins` public (#3398)
### Fixed

8
esp-hal/MIGRATING-1.0.0-beta.0.md
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@ -258,5 +258,11 @@ The data and ctrl pins of the camera have been split out into individual `with_*
)?;
+ camera.with_data0(peripherals.GPIO11).with_data1(peripherals.GPIO9).with_dataX();
```
## Configuration changes
Some configuration options are now unstable and they require the `unstable` feature to be
enabled. You can learn about a particular option in the [esp-hal documentation](https://docs.espressif.com/projects/rust/esp-hal/latest/).
The `ESP_HAL_CONFIG_PLACE_SPI_DRIVER_IN_RAM` configuration option has been renamed to `ESP_HAL_CONFIG_PLACE_SPI_MASTER_DRIVER_IN_RAM`.

6
esp-hal/build.rs
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@ -72,11 +72,11 @@ fn main() -> Result<(), Box<dyn Error>> {
"esp_hal",
&[
ConfigOption {
name: "place-spi-driver-in-ram",
description: "Places the SPI driver in RAM for better performance",
name: "place-spi-master-driver-in-ram",
description: "Places the SPI master driver in RAM for better performance",
default_value: Value::Bool(false),
constraint: None,
stability: Stability::Stable("1.0.0-beta.0"),
stability: Stability::Unstable,
active: true,
},
ConfigOption {

50
esp-hal/src/spi/master.rs
View File

@ -41,7 +41,7 @@ use core::marker::PhantomData;
#[instability::unstable]
pub use dma::*;
use enumset::{EnumSet, EnumSetType};
#[cfg(place_spi_driver_in_ram)]
#[cfg(place_spi_master_driver_in_ram)]
use procmacros::ram;
use super::{BitOrder, DataMode, DmaError, Error, Mode};
@ -1523,7 +1523,7 @@ mod dma {
///
/// The caller must ensure to not access the buffer contents while the
/// transfer is in progress. Moving the buffer itself is allowed.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
unsafe fn start_transfer_dma<RX: DmaRxBuffer, TX: DmaTxBuffer>(
&mut self,
full_duplex: bool,
@ -1724,7 +1724,7 @@ mod dma {
///
/// The caller must ensure that the buffers are not accessed while the
/// transfer is in progress. Moving the buffers is allowed.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
unsafe fn start_dma_write(
&mut self,
bytes_to_write: usize,
@ -1749,7 +1749,7 @@ mod dma {
/// SPI instance. The maximum amount of data to be sent is 32736
/// bytes.
#[allow(clippy::type_complexity)]
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
#[instability::unstable]
pub fn write<TX: DmaTxBuffer>(
mut self,
@ -1770,7 +1770,7 @@ mod dma {
///
/// The caller must ensure that the buffers are not accessed while the
/// transfer is in progress. Moving the buffers is allowed.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
unsafe fn start_dma_read(
&mut self,
bytes_to_read: usize,
@ -1785,7 +1785,7 @@ mod dma {
/// the SPI instance. The maximum amount of data to be
/// received is 32736 bytes.
#[allow(clippy::type_complexity)]
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
#[instability::unstable]
pub fn read<RX: DmaRxBuffer>(
mut self,
@ -1806,7 +1806,7 @@ mod dma {
///
/// The caller must ensure that the buffers are not accessed while the
/// transfer is in progress. Moving the buffers is allowed.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
unsafe fn start_dma_transfer(
&mut self,
bytes_to_read: usize,
@ -1823,7 +1823,7 @@ mod dma {
/// the SPI instance. The maximum amount of data to be
/// sent/received is 32736 bytes.
#[allow(clippy::type_complexity)]
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
#[instability::unstable]
pub fn transfer<RX: DmaRxBuffer, TX: DmaTxBuffer>(
mut self,
@ -1853,7 +1853,7 @@ mod dma {
///
/// The caller must ensure that the buffers are not accessed while the
/// transfer is in progress. Moving the buffers is allowed.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
unsafe fn start_half_duplex_read(
&mut self,
data_mode: DataMode,
@ -1878,7 +1878,7 @@ mod dma {
/// Perform a half-duplex read operation using DMA.
#[allow(clippy::type_complexity)]
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
#[instability::unstable]
pub fn half_duplex_read<RX: DmaRxBuffer>(
mut self,
@ -1910,7 +1910,7 @@ mod dma {
///
/// The caller must ensure that the buffers are not accessed while the
/// transfer is in progress. Moving the buffers is allowed.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
unsafe fn start_half_duplex_write(
&mut self,
data_mode: DataMode,
@ -1944,7 +1944,7 @@ mod dma {
/// Perform a half-duplex write operation using DMA.
#[allow(clippy::type_complexity)]
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
#[instability::unstable]
pub fn half_duplex_write<TX: DmaTxBuffer>(
mut self,
@ -2778,7 +2778,7 @@ impl DmaDriver {
}
#[allow(clippy::too_many_arguments)]
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
unsafe fn start_transfer_dma<Dm: DriverMode>(
&self,
_full_duplex: bool,
@ -3317,7 +3317,7 @@ impl Driver {
});
}
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn fill_fifo(&self, chunk: &[u8]) {
// TODO: replace with `array_chunks` and `from_le_bytes`
let mut c_iter = chunk.chunks_exact(4);
@ -3350,7 +3350,7 @@ impl Driver {
/// This function will return before all bytes of the last chunk to transmit
/// have been sent to the wire. If you must ensure that the whole
/// messages was written correctly, use [`Self::flush`].
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn write(&self, words: &[u8]) -> Result<(), Error> {
let num_chunks = words.len() / FIFO_SIZE;
@ -3377,7 +3377,7 @@ impl Driver {
}
/// Write bytes to SPI.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
async fn write_async(&self, words: &[u8]) -> Result<(), Error> {
// The fifo has a limited fixed size, so the data must be chunked and then
// transmitted
@ -3394,7 +3394,7 @@ impl Driver {
/// Sends out a stuffing byte for every byte to read. This function doesn't
/// perform flushing. If you want to read the response to something you
/// have written before, consider using [`Self::transfer`] instead.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn read(&self, words: &mut [u8]) -> Result<(), Error> {
let empty_array = [EMPTY_WRITE_PAD; FIFO_SIZE];
@ -3411,7 +3411,7 @@ impl Driver {
/// Sends out a stuffing byte for every byte to read. This function doesn't
/// perform flushing. If you want to read the response to something you
/// have written before, consider using [`Self::transfer`] instead.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
async fn read_async(&self, words: &mut [u8]) -> Result<(), Error> {
let empty_array = [EMPTY_WRITE_PAD; FIFO_SIZE];
@ -3428,7 +3428,7 @@ impl Driver {
/// doesn't perform flushing. If you want to read the response to
/// something you have written before, consider using [`Self::transfer`]
/// instead.
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn read_from_fifo(&self, words: &mut [u8]) -> Result<(), Error> {
let reg_block = self.regs();
@ -3452,6 +3452,7 @@ impl Driver {
}
// Check if the bus is busy and if it is wait for it to be idle
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn flush(&self) -> Result<(), Error> {
while self.busy() {
// wait for bus to be clear
@ -3459,7 +3460,7 @@ impl Driver {
Ok(())
}
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn transfer<'w>(&self, words: &'w mut [u8]) -> Result<&'w [u8], Error> {
for chunk in words.chunks_mut(FIFO_SIZE) {
self.write(chunk)?;
@ -3470,7 +3471,7 @@ impl Driver {
Ok(words)
}
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
async fn transfer_in_place_async(&self, words: &mut [u8]) -> Result<(), Error> {
for chunk in words.chunks_mut(FIFO_SIZE) {
// Cut the transfer short if the future is dropped. We'll block for a short
@ -3489,12 +3490,14 @@ impl Driver {
Ok(())
}
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn start_operation(&self) {
self.update();
self.regs().cmd().modify(|_, w| w.usr().set_bit());
}
/// Starts the operation and waits for it to complete.
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
async fn execute_operation_async(&self) {
// On ESP32, the interrupt seems to not fire in specific circumstances, when
// `listen` is called after `start_operation`. Let's call it before, to be sure.
@ -3810,7 +3813,7 @@ struct Esp32Hack {
#[cfg(esp32)]
unsafe impl Sync for Esp32Hack {}
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn handle_async(instance: impl Instance) {
let state = instance.state();
let info = instance.info();
@ -3848,7 +3851,7 @@ macro_rules! master_instance {
fn handler(&self) -> InterruptHandler {
#[$crate::handler]
#[cfg_attr(place_spi_driver_in_ram, ram)]
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn handle() {
handle_async(unsafe { $crate::peripherals::$peri::steal() })
}
@ -3881,6 +3884,7 @@ struct SpiFuture<'a> {
}
impl<'a> SpiFuture<'a> {
#[cfg_attr(place_spi_master_driver_in_ram, ram)]
fn setup(driver: &'a Driver) -> impl Future<Output = Self> {
// Make sure this is called before starting an async operation. On the ESP32,
// calling after may cause the interrupt to not fire.