itsscb/esp-hal
1
0
Fork 0
mirror of https://github.com/esp-rs/esp-hal.git synced 2025-10-03 07:05:19 +00:00
Code Issues Packages Projects Releases Wiki Activity

Panic when DefaultHandler gets invoked (#1005)

Browse Source 
* Panic when DefaultHandler gets invoked

* CHANGELOG.md

* Use EspDefaultHandler for unhandled interrupts

* `defmt`safe EspDefaultHandler
This commit is contained in:
Björn Quentin 2023-12-11 09:45:39 +01:00 committed by GitHub
parent 5b177ecc4a
commit dfad09d85c
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
8 changed files with 20 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
CHANGELOG.md
View File

@ -32,6 +32,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- Reworked construction of I2S driver instances (#983) - Reworked construction of I2S driver instances (#983)
- S2 / S3: Don't require GPIO 18 to create a USB peripheral driver instance (#990) - S2 / S3: Don't require GPIO 18 to create a USB peripheral driver instance (#990)
- Updated to latest release candidate (`1.0.0-rc.2`) for `embedded-hal{-async,-nb}` (#994) - Updated to latest release candidate (`1.0.0-rc.2`) for `embedded-hal{-async,-nb}` (#994)
- Explicit panic when hitting the `DefaultHandler` (#1005)
### Fixed ### Fixed

1
esp-hal-common/ld/esp32c2/esp32c2.x
View File

@ -14,7 +14,6 @@ PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler); PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler); PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler);
PROVIDE(__post_init = default_post_init); PROVIDE(__post_init = default_post_init);

1
esp-hal-common/ld/esp32c3/esp32c3.x
View File

@ -14,7 +14,6 @@ PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler); PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler); PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler);
PROVIDE(__post_init = default_post_init); PROVIDE(__post_init = default_post_init);

1
esp-hal-common/ld/esp32c6/esp32c6.x
View File

@ -14,7 +14,6 @@ PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler); PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler); PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler);
/* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6 has /* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6 has

1
esp-hal-common/ld/esp32h2/esp32h2.x
View File

@ -14,7 +14,6 @@ PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler); PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler); PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler); PROVIDE(ExceptionHandler = DefaultExceptionHandler);
/* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6 and ESP32-H2 have /* The ESP32-C2 and ESP32-C3 have interrupt IDs 1-31, while the ESP32-C6 and ESP32-H2 have

2
esp-hal-common/ld/riscv/hal-defaults.x
View File

@ -1,3 +1,5 @@
PROVIDE(DefaultHandler = EspDefaultHandler);
PROVIDE(interrupt1 = DefaultHandler); PROVIDE(interrupt1 = DefaultHandler);
PROVIDE(interrupt2 = DefaultHandler); PROVIDE(interrupt2 = DefaultHandler);
PROVIDE(interrupt3 = DefaultHandler); PROVIDE(interrupt3 = DefaultHandler);

2
esp-hal-common/ld/xtensa/hal-defaults.x
View File

@ -1,3 +1,5 @@
PROVIDE(DefaultHandler = EspDefaultHandler);
PROVIDE(level1_interrupt = DefaultHandler); PROVIDE(level1_interrupt = DefaultHandler);
PROVIDE(level2_interrupt = DefaultHandler); PROVIDE(level2_interrupt = DefaultHandler);
PROVIDE(level3_interrupt = DefaultHandler); PROVIDE(level3_interrupt = DefaultHandler);

20
esp-hal-common/src/lib.rs
View File

@ -161,22 +161,32 @@ pub mod trapframe {
// be directly exposed. // be directly exposed.
mod soc; mod soc;
#[cfg(xtensa)]
#[no_mangle] #[no_mangle]
extern "C" fn EspDefaultHandler(_level: u32, _interrupt: peripherals::Interrupt) { extern "C" fn EspDefaultHandler(_level: u32, _interrupt: peripherals::Interrupt) {
#[cfg(feature = "log")] #[cfg(not(feature = "defmt"))]
warn!("Unhandled level {} interrupt: {:?}", _level, _interrupt); panic!("Unhandled level {} interrupt: {:?}", _level, _interrupt);
#[cfg(feature = "defmt")] #[cfg(feature = "defmt")]
warn!( panic!(
"Unhandled level {} interrupt: {:?}", "Unhandled level {} interrupt: {:?}",
_level, _level,
defmt::Debug2Format(&_interrupt) defmt::Debug2Format(&_interrupt)
); );
} }
#[cfg(xtensa)] #[cfg(riscv)]
#[no_mangle] #[no_mangle]
extern "C" fn DefaultHandler() {} extern "C" fn EspDefaultHandler(_interrupt: peripherals::Interrupt) {
#[cfg(not(feature = "defmt"))]
panic!("Unhandled interrupt: {:?}", _interrupt);
#[cfg(feature = "defmt")]
panic!(
"Unhandled interrupt: {:?}",
defmt::Debug2Format(&_interrupt)
);
}
/// Available CPU cores /// Available CPU cores
/// ///