itsscb/esp-hal
1
0
Fork 0
mirror of https://github.com/esp-rs/esp-hal.git synced 2025-09-29 21:30:39 +00:00
Code Issues Packages Projects Releases Wiki Activity

Remove logic from InputPin and OutputPin (#2926)

Browse Source 
* Hide PAC types exposed via peripheral singletons

* Rename AlternateFunction variants

* Move logic to AnyPin

* Remove degrade_pin

* Add a note to GPIO

* Remove mask

* Fix test
This commit is contained in:
Dániel Buga 2025-01-10 15:50:03 +01:00 committed by GitHub
parent 03ea4f6c90
commit e13c09eb92
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
28 changed files with 430 additions and 522 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
esp-hal/src/gpio/etm.rs
View File

@ -181,7 +181,7 @@ impl<const C: u8> EventChannel<C> {
) -> Event<'d> {
crate::into_mapped_ref!(pin);
pin.init_input(pin_config.pull, private::Internal);
pin.init_input(pin_config.pull);
enable_event_channel(C, pin.number());
Event {
@ -289,12 +289,12 @@ impl<const C: u8> TaskChannel<C> {
) -> Task<'d> {
crate::into_mapped_ref!(pin);
pin.set_output_high(pin_config.initial_state.into(), private::Internal);
pin.set_output_high(pin_config.initial_state.into());
if pin_config.open_drain {
pin.pull_direction(pin_config.pull, private::Internal);
pin.set_to_open_drain_output(private::Internal);
pin.pull_direction(pin_config.pull);
pin.set_to_open_drain_output();
} else {
pin.set_to_push_pull_output(private::Internal);
pin.set_to_push_pull_output();
}
enable_task_channel(C, pin.number());

115
esp-hal/src/gpio/interconnect.rs
View File

@ -98,6 +98,7 @@ impl gpio::OutputSignal {
pub fn connect_to(self, pin: impl Peripheral<P = impl PeripheralOutput>) {
crate::into_mapped_ref!(pin);
// FIXME: disconnect previous connection(s)
pin.connect_peripheral_to_output(self);
}
@ -154,7 +155,7 @@ fn connect_pin_to_input_signal(
.unwrap_or(GPIO_FUNCTION)
};
pin.set_alternate_function(af, private::Internal);
pin.set_alternate_function(af);
connect_input_signal(signal, pin.number(), is_inverted, af == GPIO_FUNCTION);
}
@ -183,7 +184,7 @@ fn connect_peripheral_to_output(
signal
);
pin.set_alternate_function(af, private::Internal);
pin.set_alternate_function(af);
// Inlined because output signals can only be connected to pins or nothing, so
// there is no other user.
@ -202,7 +203,7 @@ fn connect_peripheral_to_output(
}
fn disconnect_peripheral_output_from_pin(pin: &mut AnyPin, signal: gpio::OutputSignal) {
pin.set_alternate_function(GPIO_FUNCTION, private::Internal);
pin.set_alternate_function(GPIO_FUNCTION);
unsafe { GPIO::steal() }
.func_in_sel_cfg(signal as usize - FUNC_IN_SEL_OFFSET)
@ -267,7 +268,7 @@ impl InputSignal {
/// Returns the current signal level.
pub fn level(&self) -> Level {
self.is_input_high(private::Internal).into()
self.is_input_high().into()
}
/// Inverts the peripheral's input signal.
@ -298,11 +299,11 @@ impl InputSignal {
delegate::delegate! {
#[doc(hidden)]
to self.pin {
pub fn pull_direction(&self, pull: Pull, _internal: private::Internal);
pub fn pull_direction(&self, pull: Pull);
pub fn input_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::InputSignal)];
pub fn init_input(&self, pull: Pull, _internal: private::Internal);
pub fn is_input_high(&self, _internal: private::Internal) -> bool;
pub fn enable_input(&mut self, on: bool, _internal: private::Internal);
pub fn init_input(&self, pull: Pull);
pub fn is_input_high(&self) -> bool;
pub fn enable_input(&mut self, on: bool);
}
}
}
@ -336,11 +337,11 @@ impl DirectInputSignal {
delegate::delegate! {
to self.pin {
fn pull_direction(&self, pull: Pull, _internal: private::Internal);
fn pull_direction(&self, pull: Pull);
fn input_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::InputSignal)];
fn init_input(&self, pull: Pull, _internal: private::Internal);
fn is_input_high(&self, _internal: private::Internal) -> bool;
fn enable_input(&mut self, on: bool, _internal: private::Internal);
fn init_input(&self, pull: Pull);
fn is_input_high(&self) -> bool;
fn enable_input(&mut self, on: bool);
}
}
}
@ -428,22 +429,22 @@ impl OutputSignal {
delegate::delegate! {
#[doc(hidden)]
to self.pin {
pub fn pull_direction(&self, pull: Pull, _internal: private::Internal);
pub fn pull_direction(&self, pull: Pull);
pub fn input_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::InputSignal)];
pub fn init_input(&self, pull: Pull, _internal: private::Internal);
pub fn is_input_high(&self, _internal: private::Internal) -> bool;
pub fn enable_input(&mut self, on: bool, _internal: private::Internal);
pub fn init_input(&self, pull: Pull);
pub fn is_input_high(&self) -> bool;
pub fn enable_input(&mut self, on: bool);
pub fn output_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::OutputSignal)];
pub fn set_to_open_drain_output(&mut self, _internal: private::Internal);
pub fn set_to_push_pull_output(&mut self, _internal: private::Internal);
pub fn enable_output(&mut self, on: bool, _internal: private::Internal);
pub fn set_output_high(&mut self, on: bool, _internal: private::Internal);
pub fn set_drive_strength(&mut self, strength: gpio::DriveStrength, _internal: private::Internal);
pub fn enable_open_drain(&mut self, on: bool, _internal: private::Internal);
pub fn internal_pull_up_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
pub fn internal_pull_down_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
pub fn is_set_high(&self, _internal: private::Internal) -> bool;
pub fn set_to_open_drain_output(&mut self);
pub fn set_to_push_pull_output(&mut self);
pub fn enable_output(&mut self, on: bool);
pub fn set_output_high(&mut self, on: bool);
pub fn set_drive_strength(&mut self, strength: gpio::DriveStrength);
pub fn enable_open_drain(&mut self, on: bool);
pub fn internal_pull_up_in_sleep_mode(&mut self, on: bool);
pub fn internal_pull_down_in_sleep_mode(&mut self, on: bool);
pub fn is_set_high(&self) -> bool;
}
}
}
@ -476,22 +477,22 @@ impl DirectOutputSignal {
delegate::delegate! {
to self.pin {
fn pull_direction(&self, pull: Pull, _internal: private::Internal);
fn pull_direction(&self, pull: Pull);
fn input_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::InputSignal)];
fn init_input(&self, pull: Pull, _internal: private::Internal);
fn is_input_high(&self, _internal: private::Internal) -> bool;
fn enable_input(&mut self, on: bool, _internal: private::Internal);
fn init_input(&self, pull: Pull);
fn is_input_high(&self) -> bool;
fn enable_input(&mut self, on: bool);
fn output_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::OutputSignal)];
fn set_to_open_drain_output(&mut self, _internal: private::Internal);
fn set_to_push_pull_output(&mut self, _internal: private::Internal);
fn enable_output(&mut self, on: bool, _internal: private::Internal);
fn set_output_high(&mut self, on: bool, _internal: private::Internal);
fn set_drive_strength(&mut self, strength: gpio::DriveStrength, _internal: private::Internal);
fn enable_open_drain(&mut self, on: bool, _internal: private::Internal);
fn internal_pull_up_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
fn internal_pull_down_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
fn is_set_high(&self, _internal: private::Internal) -> bool;
fn set_to_open_drain_output(&mut self);
fn set_to_push_pull_output(&mut self);
fn enable_output(&mut self, on: bool);
fn set_output_high(&mut self, on: bool);
fn set_drive_strength(&mut self, strength: gpio::DriveStrength);
fn enable_open_drain(&mut self, on: bool);
fn internal_pull_up_in_sleep_mode(&mut self, on: bool);
fn internal_pull_down_in_sleep_mode(&mut self, on: bool);
fn is_set_high(&self) -> bool;
}
}
}
@ -589,9 +590,9 @@ impl InputConnection {
InputConnectionInner::DirectInput(pin) => pin,
InputConnectionInner::Constant(level) => level,
} {
pub fn pull_direction(&self, pull: Pull, _internal: private::Internal);
pub fn init_input(&self, pull: Pull, _internal: private::Internal);
pub fn is_input_high(&self, _internal: private::Internal) -> bool;
pub fn pull_direction(&self, pull: Pull);
pub fn init_input(&self, pull: Pull);
pub fn is_input_high(&self) -> bool;
pub fn input_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::InputSignal)];
}
@ -601,7 +602,9 @@ impl InputConnection {
InputConnectionInner::DirectInput(pin) => pin,
InputConnectionInner::Constant(level) => level,
} {
pub fn enable_input(&mut self, on: bool, _internal: private::Internal);
pub fn enable_input(&mut self, on: bool);
// This doesn't need to be public, the intended way is `connect_to` and `disconnect_from`
fn connect_input_to_peripheral(&mut self, signal: gpio::InputSignal);
}
}
@ -683,10 +686,10 @@ impl OutputConnection {
OutputConnectionInner::DirectOutput(pin) => pin,
OutputConnectionInner::Constant(level) => level,
} {
pub fn is_input_high(&self, _internal: private::Internal) -> bool;
pub fn is_input_high(&self) -> bool;
pub fn input_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::InputSignal)];
pub fn is_set_high(&self, _internal: private::Internal) -> bool;
pub fn is_set_high(&self) -> bool;
pub fn output_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, gpio::OutputSignal)];
}
#[doc(hidden)]
@ -695,18 +698,20 @@ impl OutputConnection {
OutputConnectionInner::DirectOutput(pin) => pin,
OutputConnectionInner::Constant(level) => level,
} {
pub fn pull_direction(&mut self, pull: Pull, _internal: private::Internal);
pub fn init_input(&mut self, pull: Pull, _internal: private::Internal);
pub fn enable_input(&mut self, on: bool, _internal: private::Internal);
pub fn pull_direction(&mut self, pull: Pull);
pub fn init_input(&mut self, pull: Pull);
pub fn enable_input(&mut self, on: bool);
pub fn set_to_open_drain_output(&mut self, _internal: private::Internal);
pub fn set_to_push_pull_output(&mut self, _internal: private::Internal);
pub fn enable_output(&mut self, on: bool, _internal: private::Internal);
pub fn set_output_high(&mut self, on: bool, _internal: private::Internal);
pub fn set_drive_strength(&mut self, strength: gpio::DriveStrength, _internal: private::Internal);
pub fn enable_open_drain(&mut self, on: bool, _internal: private::Internal);
pub fn internal_pull_up_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
pub fn internal_pull_down_in_sleep_mode(&mut self, on: bool, _internal: private::Internal);
pub fn set_to_open_drain_output(&mut self);
pub fn set_to_push_pull_output(&mut self);
pub fn enable_output(&mut self, on: bool);
pub fn set_output_high(&mut self, on: bool);
pub fn set_drive_strength(&mut self, strength: gpio::DriveStrength);
pub fn enable_open_drain(&mut self, on: bool);
pub fn internal_pull_up_in_sleep_mode(&mut self, on: bool);
pub fn internal_pull_down_in_sleep_mode(&mut self, on: bool);
// These don't need to be public, the intended way is `connect_to` and `disconnect_from`
fn connect_peripheral_to_output(&mut self, signal: gpio::OutputSignal);
fn disconnect_from_peripheral_output(&mut self, signal: gpio::OutputSignal);
}

583
esp-hal/src/gpio/mod.rs
View File

@ -270,17 +270,17 @@ pub enum DriveStrength {
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum AlternateFunction {
/// Alternate function 0.
Function0 = 0,
_0 = 0,
/// Alternate function 1.
Function1 = 1,
_1 = 1,
/// Alternate function 2.
Function2 = 2,
_2 = 2,
/// Alternate function 3.
Function3 = 3,
_3 = 3,
/// Alternate function 4.
Function4 = 4,
_4 = 4,
/// Alternate function 5.
Function5 = 5,
_5 = 5,
}
impl TryFrom<usize> for AlternateFunction {
@ -288,12 +288,12 @@ impl TryFrom<usize> for AlternateFunction {
fn try_from(value: usize) -> Result<Self, Self::Error> {
match value {
0 => Ok(AlternateFunction::Function0),
1 => Ok(AlternateFunction::Function1),
2 => Ok(AlternateFunction::Function2),
3 => Ok(AlternateFunction::Function3),
4 => Ok(AlternateFunction::Function4),
5 => Ok(AlternateFunction::Function5),
0 => Ok(AlternateFunction::_0),
1 => Ok(AlternateFunction::_1),
2 => Ok(AlternateFunction::_2),
3 => Ok(AlternateFunction::_3),
4 => Ok(AlternateFunction::_4),
5 => Ok(AlternateFunction::_5),
_ => Err(()),
}
}
@ -348,11 +348,6 @@ pub trait Pin: Sealed {
/// GPIO number
fn number(&self) -> u8;
#[doc(hidden)]
fn mask(&self) -> u32 {
1 << (self.number() % 32)
}
/// Type-erase (degrade) this pin into an [`AnyPin`].
///
/// This converts pin singletons (`GpioPin<0>`, …), which are all different
@ -391,34 +386,7 @@ pub trait Pin: Sealed {
where
Self: Sized,
{
self.degrade_pin(private::Internal)
}
#[doc(hidden)]
fn degrade_pin(&self, _: private::Internal) -> AnyPin;
/// Enable/disable sleep-mode
#[doc(hidden)]
fn sleep_mode(&mut self, on: bool, _: private::Internal) {
io_mux_reg(self.number()).modify(|_, w| w.slp_sel().bit(on));
}
/// Configure the alternate function
#[doc(hidden)]
fn set_alternate_function(&mut self, alternate: AlternateFunction, _: private::Internal) {
io_mux_reg(self.number()).modify(|_, w| unsafe { w.mcu_sel().bits(alternate as u8) });
}
/// Enable or disable the GPIO pin output buffer.
#[doc(hidden)]
fn enable_output(&self, enable: bool, _: private::Internal) {
GpioRegisterAccess::from(self.number() as usize).write_out_en(self.mask(), enable);
}
/// Enable input for the pin
#[doc(hidden)]
fn enable_input(&mut self, on: bool, _: private::Internal) {
io_mux_reg(self.number()).modify(|_, w| w.fun_ie().bit(on));
unsafe { AnyPin::steal(self.number()) }
}
#[doc(hidden)]
@ -426,130 +394,13 @@ pub trait Pin: Sealed {
#[doc(hidden)]
fn input_signals(&self, _: private::Internal) -> &'static [(AlternateFunction, InputSignal)];
#[doc(hidden)]
fn pull_direction(&self, pull: Pull, _: private::Internal) {
let pull_up = pull == Pull::Up;
let pull_down = pull == Pull::Down;
#[cfg(esp32)]
crate::soc::gpio::errata36(self.degrade_pin(private::Internal), pull_up, pull_down);
io_mux_reg(self.number()).modify(|_, w| {
w.fun_wpd().bit(pull_down);
w.fun_wpu().bit(pull_up)
});
}
}
/// Trait implemented by pins which can be used as inputs.
pub trait InputPin: Pin + Into<AnyPin> + 'static {
/// Init as input with the given pull-up/pull-down
#[doc(hidden)]
fn init_input(&self, pull: Pull, _: private::Internal) {
self.pull_direction(pull, private::Internal);
#[cfg(usb_device)]
disable_usb_pads(self.number());
io_mux_reg(self.number()).modify(|_, w| unsafe {
w.mcu_sel().bits(GPIO_FUNCTION as u8);
w.fun_ie().set_bit();
w.slp_sel().clear_bit()
});
}
/// The current state of the input
#[doc(hidden)]
fn is_input_high(&self, _: private::Internal) -> bool {
GpioRegisterAccess::from(self.number() as usize).read_input() & self.mask() != 0
}
}
pub trait InputPin: Pin + Into<AnyPin> + 'static {}
/// Trait implemented by pins which can be used as outputs.
pub trait OutputPin: Pin + Into<AnyPin> + 'static {
/// Set up as output
#[doc(hidden)]
fn init_output(
&mut self,
alternate: AlternateFunction,
open_drain: bool,
input_enable: Option<bool>,
_: private::Internal,
) {
self.enable_output(true, private::Internal);
let gpio = unsafe { GPIO::steal() };
gpio.pin(self.number() as usize)
.modify(|_, w| w.pad_driver().bit(open_drain));
gpio.func_out_sel_cfg(self.number() as usize)
.modify(|_, w| unsafe { w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) });
#[cfg(usb_device)]
disable_usb_pads(self.number());
io_mux_reg(self.number()).modify(|_, w| unsafe {
w.mcu_sel().bits(alternate as u8);
if let Some(input_enable) = input_enable {
w.fun_ie().bit(input_enable);
}
w.fun_drv().bits(DriveStrength::_20mA as u8);
w.slp_sel().clear_bit()
});
}
/// Configure open-drain mode
#[doc(hidden)]
fn set_to_open_drain_output(&mut self, _: private::Internal) {
self.init_output(GPIO_FUNCTION, true, Some(true), private::Internal);
}
/// Configure output mode
#[doc(hidden)]
fn set_to_push_pull_output(&mut self, _: private::Internal) {
self.init_output(GPIO_FUNCTION, false, None, private::Internal);
}
/// Set the pin's level to high or low
#[doc(hidden)]
fn set_output_high(&mut self, high: bool, _: private::Internal) {
GpioRegisterAccess::from(self.number() as usize).write_output(self.mask(), high);
}
/// Configure the [DriveStrength] of the pin
#[doc(hidden)]
fn set_drive_strength(&mut self, strength: DriveStrength, _: private::Internal) {
io_mux_reg(self.number()).modify(|_, w| unsafe { w.fun_drv().bits(strength as u8) });
}
/// Enable/disable open-drain mode
#[doc(hidden)]
fn enable_open_drain(&mut self, on: bool, _: private::Internal) {
unsafe { GPIO::steal() }
.pin(self.number() as usize)
.modify(|_, w| w.pad_driver().bit(on));
}
/// Configure internal pull-up resistor in sleep mode
#[doc(hidden)]
fn internal_pull_up_in_sleep_mode(&mut self, on: bool, _: private::Internal) {
io_mux_reg(self.number()).modify(|_, w| w.mcu_wpu().bit(on));
}
/// Configure internal pull-down resistor in sleep mode
#[doc(hidden)]
fn internal_pull_down_in_sleep_mode(&mut self, on: bool, _: private::Internal) {
io_mux_reg(self.number()).modify(|_, w| w.mcu_wpd().bit(on));
}
/// Is the output set to high
#[doc(hidden)]
fn is_set_high(&self, _: private::Internal) -> bool {
GpioRegisterAccess::from(self.number() as usize).read_output() & self.mask() != 0
}
}
pub trait OutputPin: Pin + Into<AnyPin> + 'static {}
/// Trait implemented by pins which can be used as analog pins
#[instability::unstable]
@ -821,10 +672,10 @@ where
/// external hardware.
#[instability::unstable]
pub fn split(self) -> (interconnect::InputSignal, interconnect::OutputSignal) {
(
interconnect::InputSignal::new(self.degrade_pin(private::Internal)),
interconnect::OutputSignal::new(self.degrade_pin(private::Internal)),
)
// FIXME: we should implement this in the gpio macro for output pins, but we
// should also have an input-only alternative for pins that can't be used as
// outputs.
self.degrade().split()
}
}
@ -1076,16 +927,12 @@ macro_rules! gpio {
$gpionum
}
fn degrade_pin(&self, _: $crate::private::Internal) -> $crate::gpio::AnyPin {
$crate::gpio::AnyPin($gpionum)
}
fn output_signals(&self, _: $crate::private::Internal) -> &'static [($crate::gpio::AlternateFunction, $crate::gpio::OutputSignal)] {
&[
$(
$(
(
$crate::gpio::AlternateFunction::[< Function $af_output_num >],
$crate::gpio::AlternateFunction::[< _ $af_output_num >],
$crate::gpio::OutputSignal::$af_output_signal
),
)*
@ -1098,7 +945,7 @@ macro_rules! gpio {
$(
$(
(
$crate::gpio::AlternateFunction::[< Function $af_input_num >],
$crate::gpio::AlternateFunction::[< _ $af_input_num >],
$crate::gpio::InputSignal::$af_input_signal
),
)*
@ -1814,15 +1661,15 @@ impl<'d> Flex<'d> {
#[inline]
#[instability::unstable]
pub fn peripheral_input(&self) -> interconnect::InputSignal {
self.pin.degrade_pin(private::Internal).split().0
unsafe { AnyPin::steal(self.number()) }.split().0
}
/// Set the GPIO to input mode.
#[inline]
#[instability::unstable]
pub fn set_as_input(&mut self, pull: Pull) {
self.pin.init_input(pull, private::Internal);
self.pin.enable_output(false, private::Internal);
self.pin.init_input(pull);
self.pin.enable_output(false);
}
/// Get whether the pin input level is high.
@ -1843,7 +1690,7 @@ impl<'d> Flex<'d> {
#[inline]
#[instability::unstable]
pub fn level(&self) -> Level {
self.pin.is_input_high(private::Internal).into()
self.pin.is_input_high().into()
}
fn listen_with_options(
@ -1927,7 +1774,7 @@ impl<'d> Flex<'d> {
#[inline]
#[instability::unstable]
pub fn set_as_output(&mut self) {
self.pin.set_to_push_pull_output(private::Internal);
self.pin.set_to_push_pull_output();
}
/// Set the output as high.
@ -1948,7 +1795,7 @@ impl<'d> Flex<'d> {
#[inline]
#[instability::unstable]
pub fn set_level(&mut self, level: Level) {
self.pin.set_output_high(level.into(), private::Internal);
self.pin.set_output_high(level.into());
}
/// Is the output pin set as high?
@ -1969,7 +1816,7 @@ impl<'d> Flex<'d> {
#[inline]
#[instability::unstable]
pub fn output_level(&self) -> Level {
self.pin.is_set_high(private::Internal).into()
self.pin.is_set_high().into()
}
/// Toggle pin output
@ -1984,15 +1831,15 @@ impl<'d> Flex<'d> {
#[inline]
#[instability::unstable]
pub fn set_drive_strength(&mut self, strength: DriveStrength) {
self.pin.set_drive_strength(strength, private::Internal);
self.pin.set_drive_strength(strength);
}
/// Set the GPIO to open-drain mode.
#[inline]
#[instability::unstable]
pub fn set_as_open_drain(&mut self, pull: Pull) {
self.pin.set_to_open_drain_output(private::Internal);
self.pin.pull_direction(pull, private::Internal);
self.pin.set_to_open_drain_output();
self.pin.pull_direction(pull);
}
/// Split the pin into an input and output signal.
@ -2003,7 +1850,7 @@ impl<'d> Flex<'d> {
#[instability::unstable]
pub fn split(self) -> (interconnect::InputSignal, interconnect::OutputSignal) {
assert!(self.pin.is_output());
self.pin.degrade_pin(private::Internal).split()
unsafe { AnyPin::steal(self.number()) }.split()
}
/// Turns the pin object into a peripheral
@ -2025,7 +1872,6 @@ impl Pin for Flex<'_> {
delegate::delegate! {
to self.pin {
fn number(&self) -> u8;
fn degrade_pin(&self, _internal: private::Internal) -> AnyPin;
fn output_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, OutputSignal)];
fn input_signals(&self, _internal: private::Internal) -> &'static [(AlternateFunction, InputSignal)];
}
@ -2055,169 +1901,232 @@ impl RtcPinWithResistors for Flex<'_> {
}
}
pub(crate) mod internal {
use super::*;
impl private::Sealed for AnyPin {}
impl private::Sealed for AnyPin {}
impl AnyPin {
/// Init as input with the given pull-up/pull-down
#[inline]
pub(crate) fn init_input(&self, pull: Pull) {
self.pull_direction(pull);
impl AnyPin {
/// Split the pin into an input and output signal.
///
/// Peripheral signals allow connecting peripherals together without
/// using external hardware.
#[inline]
#[allow(unused_braces, reason = "False positive")]
#[instability::unstable]
pub fn split(self) -> (interconnect::InputSignal, interconnect::OutputSignal) {
handle_gpio_input!(self, target, { target.split() })
}
#[cfg(usb_device)]
disable_usb_pads(self.number());
io_mux_reg(self.number()).modify(|_, w| unsafe {
w.mcu_sel().bits(GPIO_FUNCTION as u8);
w.fun_ie().set_bit();
w.slp_sel().clear_bit()
});
}
impl Pin for AnyPin {
#[inline(always)]
fn number(&self) -> u8 {
self.0
}
fn degrade_pin(&self, _: private::Internal) -> AnyPin {
unsafe { self.clone_unchecked() }
}
fn sleep_mode(&mut self, on: bool, _: private::Internal) {
handle_gpio_input!(self, target, {
Pin::sleep_mode(&mut target, on, private::Internal)
})
}
fn set_alternate_function(&mut self, alternate: AlternateFunction, _: private::Internal) {
handle_gpio_input!(self, target, {
Pin::set_alternate_function(&mut target, alternate, private::Internal)
})
}
fn output_signals(
&self,
_: private::Internal,
) -> &'static [(AlternateFunction, OutputSignal)] {
handle_gpio_output!(self, target, {
Pin::output_signals(&target, private::Internal)
})
}
fn input_signals(
&self,
_: private::Internal,
) -> &'static [(AlternateFunction, InputSignal)] {
handle_gpio_input!(self, target, {
Pin::input_signals(&target, private::Internal)
})
}
/// Split the pin into an input and output signal.
///
/// Peripheral signals allow connecting peripherals together without
/// using external hardware.
#[inline]
#[instability::unstable]
pub fn split(self) -> (interconnect::InputSignal, interconnect::OutputSignal) {
assert!(self.is_output());
(
interconnect::InputSignal::new(Self(self.0)),
interconnect::OutputSignal::new(Self(self.0)),
)
}
impl InputPin for AnyPin {}
// Need to forward these one by one because not all pins support all functions.
impl OutputPin for AnyPin {
fn init_output(
&mut self,
alternate: AlternateFunction,
open_drain: bool,
input_enable: Option<bool>,
_: private::Internal,
) {
handle_gpio_output!(self, target, {
OutputPin::init_output(
&mut target,
alternate,
open_drain,
input_enable,
private::Internal,
)
})
}
fn set_to_open_drain_output(&mut self, _: private::Internal) {
handle_gpio_output!(self, target, {
OutputPin::set_to_open_drain_output(&mut target, private::Internal)
})
}
fn set_to_push_pull_output(&mut self, _: private::Internal) {
handle_gpio_output!(self, target, {
OutputPin::set_to_push_pull_output(&mut target, private::Internal)
})
}
// We use the default `set_output_high` implementation to avoid matching on pin
// type. We check the pin type to enable output functionality anyway.
fn set_drive_strength(&mut self, strength: DriveStrength, _: private::Internal) {
handle_gpio_output!(self, target, {
OutputPin::set_drive_strength(&mut target, strength, private::Internal)
})
}
fn enable_open_drain(&mut self, on: bool, _: private::Internal) {
handle_gpio_output!(self, target, {
OutputPin::enable_open_drain(&mut target, on, private::Internal)
})
}
fn internal_pull_up_in_sleep_mode(&mut self, on: bool, _: private::Internal) {
handle_gpio_output!(self, target, {
OutputPin::internal_pull_up_in_sleep_mode(&mut target, on, private::Internal)
})
}
fn internal_pull_down_in_sleep_mode(&mut self, on: bool, _: private::Internal) {
handle_gpio_output!(self, target, {
OutputPin::internal_pull_down_in_sleep_mode(&mut target, on, private::Internal)
})
}
#[inline]
pub(crate) fn set_alternate_function(&self, alternate: AlternateFunction) {
io_mux_reg(self.number()).modify(|_, w| unsafe { w.mcu_sel().bits(alternate as u8) });
}
#[cfg(any(lp_io, rtc_cntl))]
impl RtcPin for AnyPin {
#[cfg(xtensa)]
#[allow(unused_braces)] // False positive :/
fn rtc_number(&self) -> u8 {
handle_rtcio!(self, target, { RtcPin::rtc_number(&target) })
}
// /// Enable/disable sleep-mode
// #[inline]
// fn sleep_mode(&mut self, on: bool, _: private::Internal) {
// io_mux_reg(self.number()).modify(|_, w| w.slp_sel().bit(on));
// }
#[cfg(any(xtensa, esp32c6))]
fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: RtcFunction) {
handle_rtcio!(self, target, {
RtcPin::rtc_set_config(&mut target, input_enable, mux, func)
})
}
fn rtcio_pad_hold(&mut self, enable: bool) {
handle_rtcio!(self, target, {
RtcPin::rtcio_pad_hold(&mut target, enable)
})
}
#[cfg(any(esp32c2, esp32c3, esp32c6))]
unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) {
handle_rtcio!(self, target, {
RtcPin::apply_wakeup(&mut target, wakeup, level)
})
}
/// Enable or disable the GPIO pin output buffer.
#[inline]
pub(crate) fn enable_output(&self, enable: bool) {
assert!(self.is_output() || !enable);
GpioRegisterAccess::from(self.number() as usize).write_out_en(self.mask(), enable);
}
#[cfg(any(lp_io, rtc_cntl))]
impl RtcPinWithResistors for AnyPin {
fn rtcio_pullup(&mut self, enable: bool) {
handle_rtcio_with_resistors!(self, target, {
RtcPinWithResistors::rtcio_pullup(&mut target, enable)
})
}
/// Enable input for the pin
#[inline]
pub(crate) fn enable_input(&self, on: bool) {
io_mux_reg(self.number()).modify(|_, w| w.fun_ie().bit(on));
}
fn rtcio_pulldown(&mut self, enable: bool) {
handle_rtcio_with_resistors!(self, target, {
RtcPinWithResistors::rtcio_pulldown(&mut target, enable)
})
}
#[inline]
pub(crate) fn pull_direction(&self, pull: Pull) {
let pull_up = pull == Pull::Up;
let pull_down = pull == Pull::Down;
#[cfg(esp32)]
crate::soc::gpio::errata36(Self(self.0), pull_up, pull_down);
io_mux_reg(self.number()).modify(|_, w| {
w.fun_wpd().bit(pull_down);
w.fun_wpu().bit(pull_up)
});
}
#[inline]
fn mask(&self) -> u32 {
1 << (self.number() % 32)
}
/// The current state of the input
#[inline]
pub(crate) fn is_input_high(&self) -> bool {
GpioRegisterAccess::from(self.number() as usize).read_input() & self.mask() != 0
}
/// Set up as output
#[inline]
pub(crate) fn init_output(
&mut self,
alternate: AlternateFunction,
open_drain: bool,
input_enable: Option<bool>,
) {
self.enable_output(true);
let gpio = unsafe { GPIO::steal() };
gpio.pin(self.number() as usize)
.modify(|_, w| w.pad_driver().bit(open_drain));
gpio.func_out_sel_cfg(self.number() as usize)
.modify(|_, w| unsafe { w.out_sel().bits(OutputSignal::GPIO as OutputSignalType) });
#[cfg(usb_device)]
disable_usb_pads(self.number());
io_mux_reg(self.number()).modify(|_, w| unsafe {
w.mcu_sel().bits(alternate as u8);
if let Some(input_enable) = input_enable {
w.fun_ie().bit(input_enable);
}
w.fun_drv().bits(DriveStrength::_20mA as u8);
w.slp_sel().clear_bit()
});
}
/// Configure open-drain mode
#[inline]
pub(crate) fn set_to_open_drain_output(&mut self) {
self.init_output(GPIO_FUNCTION, true, Some(true));
}
/// Configure output mode
#[inline]
pub(crate) fn set_to_push_pull_output(&mut self) {
self.init_output(GPIO_FUNCTION, false, None);
}
/// Set the pin's level to high or low
#[inline]
pub(crate) fn set_output_high(&mut self, high: bool) {
GpioRegisterAccess::from(self.number() as usize).write_output(self.mask(), high);
}
/// Configure the [DriveStrength] of the pin
#[inline]
pub(crate) fn set_drive_strength(&mut self, strength: DriveStrength) {
io_mux_reg(self.number()).modify(|_, w| unsafe { w.fun_drv().bits(strength as u8) });
}
/// Enable/disable open-drain mode
#[inline]
pub(crate) fn enable_open_drain(&mut self, on: bool) {
unsafe { GPIO::steal() }
.pin(self.number() as usize)
.modify(|_, w| w.pad_driver().bit(on));
}
/// Configure internal pull-up resistor in sleep mode
#[inline]
pub(crate) fn internal_pull_up_in_sleep_mode(&mut self, on: bool) {
io_mux_reg(self.number()).modify(|_, w| w.mcu_wpu().bit(on));
}
/// Configure internal pull-down resistor in sleep mode
#[inline]
pub(crate) fn internal_pull_down_in_sleep_mode(&mut self, on: bool) {
io_mux_reg(self.number()).modify(|_, w| w.mcu_wpd().bit(on));
}
/// Is the output set to high
#[inline]
pub(crate) fn is_set_high(&self) -> bool {
GpioRegisterAccess::from(self.number() as usize).read_output() & self.mask() != 0
}
}
impl Pin for AnyPin {
#[inline(always)]
fn number(&self) -> u8 {
self.0
}
fn output_signals(&self, _: private::Internal) -> &'static [(AlternateFunction, OutputSignal)] {
handle_gpio_output!(self, target, {
Pin::output_signals(&target, private::Internal)
})
}
fn input_signals(&self, _: private::Internal) -> &'static [(AlternateFunction, InputSignal)] {
handle_gpio_input!(self, target, {
Pin::input_signals(&target, private::Internal)
})
}
}
impl InputPin for AnyPin {}
impl OutputPin for AnyPin {}
#[cfg(any(lp_io, rtc_cntl))]
impl RtcPin for AnyPin {
#[cfg(xtensa)]
#[allow(unused_braces)] // False positive :/
fn rtc_number(&self) -> u8 {
handle_rtcio!(self, target, { RtcPin::rtc_number(&target) })
}
#[cfg(any(xtensa, esp32c6))]
fn rtc_set_config(&mut self, input_enable: bool, mux: bool, func: RtcFunction) {
handle_rtcio!(self, target, {
RtcPin::rtc_set_config(&mut target, input_enable, mux, func)
})
}
fn rtcio_pad_hold(&mut self, enable: bool) {
handle_rtcio!(self, target, {
RtcPin::rtcio_pad_hold(&mut target, enable)
})
}
#[cfg(any(esp32c2, esp32c3, esp32c6))]
unsafe fn apply_wakeup(&mut self, wakeup: bool, level: u8) {
handle_rtcio!(self, target, {
RtcPin::apply_wakeup(&mut target, wakeup, level)
})
}
}
#[cfg(any(lp_io, rtc_cntl))]
impl RtcPinWithResistors for AnyPin {
fn rtcio_pullup(&mut self, enable: bool) {
handle_rtcio_with_resistors!(self, target, {
RtcPinWithResistors::rtcio_pullup(&mut target, enable)
})
}
fn rtcio_pulldown(&mut self, enable: bool) {
handle_rtcio_with_resistors!(self, target, {
RtcPinWithResistors::rtcio_pulldown(&mut target, enable)
})
}
}

26
esp-hal/src/gpio/placeholder.rs
View File

@ -17,7 +17,7 @@ impl crate::peripheral::Peripheral for Level {
}
impl Level {
pub(crate) fn pull_direction(&self, _pull: Pull, _internal: private::Internal) {}
pub(crate) fn pull_direction(&self, _pull: Pull) {}
pub(crate) fn input_signals(
&self,
@ -26,11 +26,11 @@ impl Level {
&[]
}
pub(crate) fn init_input(&self, _pull: Pull, _: private::Internal) {}
pub(crate) fn init_input(&self, _pull: Pull) {}
pub(crate) fn enable_input(&mut self, _on: bool, _: private::Internal) {}
pub(crate) fn enable_input(&mut self, _on: bool) {}
pub(crate) fn is_input_high(&self, _: private::Internal) -> bool {
pub(crate) fn is_input_high(&self) -> bool {
*self == Level::High
}
@ -44,16 +44,16 @@ impl Level {
connect_input_signal(signal, value, false, true);
}
pub(crate) fn set_to_open_drain_output(&mut self, _: private::Internal) {}
pub(crate) fn set_to_push_pull_output(&mut self, _: private::Internal) {}
pub(crate) fn enable_output(&mut self, _on: bool, _: private::Internal) {}
pub(crate) fn set_output_high(&mut self, _on: bool, _: private::Internal) {}
pub(crate) fn set_drive_strength(&mut self, _strength: DriveStrength, _: private::Internal) {}
pub(crate) fn enable_open_drain(&mut self, _on: bool, _: private::Internal) {}
pub(crate) fn internal_pull_up_in_sleep_mode(&mut self, _on: bool, _: private::Internal) {}
pub(crate) fn internal_pull_down_in_sleep_mode(&mut self, _on: bool, _: private::Internal) {}
pub(crate) fn set_to_open_drain_output(&mut self) {}
pub(crate) fn set_to_push_pull_output(&mut self) {}
pub(crate) fn enable_output(&mut self, _on: bool) {}
pub(crate) fn set_output_high(&mut self, _on: bool) {}
pub(crate) fn set_drive_strength(&mut self, _strength: DriveStrength) {}
pub(crate) fn enable_open_drain(&mut self, _on: bool) {}
pub(crate) fn internal_pull_up_in_sleep_mode(&mut self, _on: bool) {}
pub(crate) fn internal_pull_down_in_sleep_mode(&mut self, _on: bool) {}
pub(crate) fn is_set_high(&self, _: private::Internal) -> bool {
pub(crate) fn is_set_high(&self) -> bool {
false
}

8
esp-hal/src/i2c/master/mod.rs
View File

@ -493,11 +493,11 @@ impl<'d, Dm: DriverMode> I2c<'d, Dm> {
) -> Self {
crate::into_mapped_ref!(pin);
// avoid the pin going low during configuration
pin.set_output_high(true, private::Internal);
pin.set_output_high(true);
pin.set_to_open_drain_output(private::Internal);
pin.enable_input(true, private::Internal);
pin.pull_direction(Pull::Up, private::Internal);
pin.set_to_open_drain_output();
pin.enable_input(true);
pin.pull_direction(Pull::Up);
input.connect_to(&mut pin);
output.connect_to(&mut pin);

15
esp-hal/src/i2s/master.rs
View File

@ -387,7 +387,7 @@ where
/// Configures the I2S peripheral to use a master clock (MCLK) output pin.
pub fn with_mclk<P: PeripheralOutput>(self, pin: impl Peripheral<P = P> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
self.i2s_tx.i2s.mclk_signal().connect_to(pin);
self
@ -684,7 +684,6 @@ mod private {
interrupt::InterruptHandler,
peripheral::{Peripheral, PeripheralRef},
peripherals::{Interrupt, I2S0},
private,
DriverMode,
};
@ -717,7 +716,7 @@ mod private {
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(private::Internal);
pin.set_to_push_pull_output();
self.i2s.bclk_signal().connect_to(pin);
self
@ -728,7 +727,7 @@ mod private {
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(private::Internal);
pin.set_to_push_pull_output();
self.i2s.ws_signal().connect_to(pin);
self
@ -739,7 +738,7 @@ mod private {
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(private::Internal);
pin.set_to_push_pull_output();
self.i2s.dout_signal().connect_to(pin);
self
@ -775,7 +774,7 @@ mod private {
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(private::Internal);
pin.set_to_push_pull_output();
self.i2s.bclk_rx_signal().connect_to(pin);
self
@ -786,7 +785,7 @@ mod private {
P: PeripheralOutput,
{
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(private::Internal);
pin.set_to_push_pull_output();
self.i2s.ws_rx_signal().connect_to(pin);
self
@ -797,7 +796,7 @@ mod private {
P: PeripheralInput,
{
crate::into_mapped_ref!(pin);
pin.init_input(crate::gpio::Pull::None, private::Internal);
pin.init_input(crate::gpio::Pull::None);
self.i2s.din_signal().connect_to(pin);
self

7
esp-hal/src/i2s/parallel.rs
View File

@ -123,7 +123,6 @@ use crate::{
},
peripheral::{Peripheral, PeripheralRef},
peripherals::{i2s0::RegisterBlock, I2S0, I2S1},
private::Internal,
system::PeripheralGuard,
Async,
Blocking,
@ -186,7 +185,7 @@ impl<'d> TxPins<'d> for TxSixteenBits<'d> {
crate::into_ref!(instance);
let bits = self.bus_width();
for (i, pin) in self.pins.iter_mut().enumerate() {
pin.set_to_push_pull_output(Internal);
pin.set_to_push_pull_output();
instance.data_out_signal(i, bits).connect_to(pin);
}
}
@ -228,7 +227,7 @@ impl<'d> TxPins<'d> for TxEightBits<'d> {
crate::into_ref!(instance);
let bits = self.bus_width();
for (i, pin) in self.pins.iter_mut().enumerate() {
pin.set_to_push_pull_output(Internal);
pin.set_to_push_pull_output();
instance.data_out_signal(i, bits).connect_to(pin);
}
}
@ -267,7 +266,7 @@ impl<'d> I2sParallel<'d, Blocking> {
// configure the I2S peripheral for parallel mode
i2s.setup(frequency, pins.bus_width());
// setup the clock pin
clock_pin.set_to_push_pull_output(Internal);
clock_pin.set_to_push_pull_output();
i2s.ws_signal().connect_to(clock_pin);
pins.configure(i2s.reborrow());

18
esp-hal/src/lcd_cam/cam.rs
View File

@ -227,7 +227,7 @@ impl<'d> Camera<'d> {
) -> Self {
crate::into_mapped_ref!(mclk);
mclk.set_to_push_pull_output(crate::private::Internal);
mclk.set_to_push_pull_output();
OutputSignal::CAM_CLK.connect_to(mclk);
self
@ -240,7 +240,7 @@ impl<'d> Camera<'d> {
) -> Self {
crate::into_mapped_ref!(pclk);
pclk.init_input(Pull::None, crate::private::Internal);
pclk.init_input(Pull::None);
InputSignal::CAM_PCLK.connect_to(pclk);
self
@ -255,9 +255,9 @@ impl<'d> Camera<'d> {
) -> Self {
crate::into_mapped_ref!(vsync, h_enable);
vsync.init_input(Pull::None, crate::private::Internal);
vsync.init_input(Pull::None);
InputSignal::CAM_V_SYNC.connect_to(vsync);
h_enable.init_input(Pull::None, crate::private::Internal);
h_enable.init_input(Pull::None);
InputSignal::CAM_H_ENABLE.connect_to(h_enable);
self.lcd_cam
@ -281,11 +281,11 @@ impl<'d> Camera<'d> {
) -> Self {
crate::into_mapped_ref!(vsync, hsync, h_enable);
vsync.init_input(Pull::None, crate::private::Internal);
vsync.init_input(Pull::None);
InputSignal::CAM_V_SYNC.connect_to(vsync);
hsync.init_input(Pull::None, crate::private::Internal);
hsync.init_input(Pull::None);
InputSignal::CAM_H_SYNC.connect_to(hsync);
h_enable.init_input(Pull::None, crate::private::Internal);
h_enable.init_input(Pull::None);
InputSignal::CAM_H_ENABLE.connect_to(h_enable);
self.lcd_cam
@ -500,7 +500,7 @@ impl RxEightBits {
];
for (pin, signal) in pairs.into_iter() {
pin.init_input(Pull::None, crate::private::Internal);
pin.init_input(Pull::None);
signal.connect_to(pin);
}
@ -577,7 +577,7 @@ impl RxSixteenBits {
];
for (pin, signal) in pairs.into_iter() {
pin.init_input(Pull::None, crate::private::Internal);
pin.init_input(Pull::None);
signal.connect_to(pin);
}

40
esp-hal/src/lcd_cam/lcd/dpi.rs
View File

@ -306,7 +306,7 @@ where
/// signal.
pub fn with_vsync<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_V_SYNC.connect_to(pin);
self
@ -318,7 +318,7 @@ where
/// signal.
pub fn with_hsync<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_H_SYNC.connect_to(pin);
self
@ -330,7 +330,7 @@ where
/// signal.
pub fn with_de<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_H_ENABLE.connect_to(pin);
self
@ -342,7 +342,7 @@ where
/// signal.
pub fn with_pclk<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_PCLK.connect_to(pin);
self
@ -354,7 +354,7 @@ where
/// signal.
pub fn with_data0<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_0.connect_to(pin);
self
@ -366,7 +366,7 @@ where
/// signal.
pub fn with_data1<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_1.connect_to(pin);
self
@ -378,7 +378,7 @@ where
/// signal.
pub fn with_data2<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_2.connect_to(pin);
self
@ -390,7 +390,7 @@ where
/// signal.
pub fn with_data3<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_3.connect_to(pin);
self
@ -402,7 +402,7 @@ where
/// signal.
pub fn with_data4<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_4.connect_to(pin);
self
@ -414,7 +414,7 @@ where
/// signal.
pub fn with_data5<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_5.connect_to(pin);
self
@ -426,7 +426,7 @@ where
/// signal.
pub fn with_data6<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_6.connect_to(pin);
self
@ -438,7 +438,7 @@ where
/// signal.
pub fn with_data7<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_7.connect_to(pin);
self
@ -450,7 +450,7 @@ where
/// signal.
pub fn with_data8<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_8.connect_to(pin);
self
@ -462,7 +462,7 @@ where
/// signal.
pub fn with_data9<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_9.connect_to(pin);
self
@ -474,7 +474,7 @@ where
/// DATA_10 signal.
pub fn with_data10<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_10.connect_to(pin);
self
@ -486,7 +486,7 @@ where
/// DATA_11 signal.
pub fn with_data11<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_11.connect_to(pin);
self
@ -498,7 +498,7 @@ where
/// DATA_12 signal.
pub fn with_data12<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_12.connect_to(pin);
self
@ -510,7 +510,7 @@ where
/// DATA_13 signal.
pub fn with_data13<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_13.connect_to(pin);
self
@ -522,7 +522,7 @@ where
/// DATA_14 signal.
pub fn with_data14<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_14.connect_to(pin);
self
@ -534,7 +534,7 @@ where
/// DATA_15 signal.
pub fn with_data15<S: PeripheralOutput>(self, pin: impl Peripheral<P = S> + 'd) -> Self {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
OutputSignal::LCD_DATA_15.connect_to(pin);
self

10
esp-hal/src/lcd_cam/lcd/i8080.rs
View File

@ -264,7 +264,7 @@ where
/// Associates a CS pin with the I8080 interface.
pub fn with_cs<CS: PeripheralOutput>(self, cs: impl Peripheral<P = CS> + 'd) -> Self {
crate::into_mapped_ref!(cs);
cs.set_to_push_pull_output(crate::private::Internal);
cs.set_to_push_pull_output();
OutputSignal::LCD_CS.connect_to(cs);
self
@ -278,10 +278,10 @@ where
) -> Self {
crate::into_mapped_ref!(dc, wrx);
dc.set_to_push_pull_output(crate::private::Internal);
dc.set_to_push_pull_output();
OutputSignal::LCD_DC.connect_to(dc);
wrx.set_to_push_pull_output(crate::private::Internal);
wrx.set_to_push_pull_output();
OutputSignal::LCD_PCLK.connect_to(wrx);
self
@ -659,7 +659,7 @@ impl TxPins for TxEightBits<'_> {
];
for (pin, signal) in self.pins.iter_mut().zip(SIGNALS.into_iter()) {
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
signal.connect_to(pin);
}
}
@ -728,7 +728,7 @@ impl TxPins for TxSixteenBits<'_> {
];
for (pin, signal) in self.pins.iter_mut().zip(SIGNALS.into_iter()) {
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
signal.connect_to(pin);
}
}

8
esp-hal/src/ledc/channel.rs
View File

@ -563,12 +563,8 @@ where
}
match cfg {
config::PinConfig::PushPull => self
.output_pin
.set_to_push_pull_output(crate::private::Internal),
config::PinConfig::OpenDrain => self
.output_pin
.set_to_open_drain_output(crate::private::Internal),
config::PinConfig::PushPull => self.output_pin.set_to_push_pull_output(),
config::PinConfig::OpenDrain => self.output_pin.set_to_open_drain_output(),
};
let timer_number = timer.number() as u8;

3
esp-hal/src/mcpwm/operator.rs
View File

@ -16,7 +16,6 @@ use crate::{
gpio::interconnect::{OutputConnection, PeripheralOutput},
mcpwm::{timer::Timer, PwmPeripheral},
peripheral::{Peripheral, PeripheralRef},
private,
};
/// Input/Output Stream descriptor for each channel
@ -310,7 +309,7 @@ impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP,
pin.set_update_method(config.update_method);
PWM::output_signal::<OP, IS_A>().connect_to(&mut pin.pin);
pin.pin.enable_output(true, private::Internal);
pin.pin.enable_output(true);
pin
}

18
esp-hal/src/parl_io.rs
View File

@ -390,7 +390,7 @@ impl<'d> ClkOutPin<'d> {
}
impl TxClkPin for ClkOutPin<'_> {
fn configure(&mut self) {
self.pin.set_to_push_pull_output(crate::private::Internal);
self.pin.set_to_push_pull_output();
crate::gpio::OutputSignal::PARL_TX_CLK.connect_to(&mut self.pin);
}
}
@ -412,8 +412,7 @@ impl TxClkPin for ClkInPin<'_> {
pcr.parl_clk_tx_conf()
.modify(|_, w| unsafe { w.parl_clk_tx_sel().bits(3).parl_clk_tx_div_num().bits(0) }); // PAD_CLK_TX, no divider
self.pin
.init_input(crate::gpio::Pull::None, crate::private::Internal);
self.pin.init_input(crate::gpio::Pull::None);
crate::gpio::InputSignal::PARL_TX_CLK.connect_to(&mut self.pin);
}
}
@ -439,8 +438,7 @@ impl RxClkPin for RxClkInPin<'_> {
pcr.parl_clk_rx_conf()
.modify(|_, w| unsafe { w.parl_clk_rx_sel().bits(3).parl_clk_rx_div_num().bits(0) }); // PAD_CLK_TX, no divider
self.pin
.init_input(crate::gpio::Pull::None, crate::private::Internal);
self.pin.init_input(crate::gpio::Pull::None);
crate::gpio::InputSignal::PARL_RX_CLK.connect_to(&mut self.pin);
Instance::set_rx_clk_edge_sel(self.sample_edge);
@ -478,8 +476,7 @@ where
{
fn configure(&mut self) -> Result<(), Error> {
self.tx_pins.configure()?;
self.valid_pin
.set_to_push_pull_output(crate::private::Internal);
self.valid_pin.set_to_push_pull_output();
Instance::tx_valid_pin_signal().connect_to(&mut self.valid_pin);
Instance::set_tx_hw_valid_en(true);
Ok(())
@ -550,7 +547,7 @@ macro_rules! tx_pins {
{
fn configure(&mut self) -> Result<(), Error>{
$(
self.[< pin_ $pin:lower >].set_to_push_pull_output(crate::private::Internal);
self.[< pin_ $pin:lower >].set_to_push_pull_output();
crate::gpio::OutputSignal::$signal.connect_to(&mut self.[< pin_ $pin:lower >]);
)+
@ -669,8 +666,7 @@ where
{
fn configure(&mut self) -> Result<(), Error> {
self.rx_pins.configure()?;
self.valid_pin
.init_input(crate::gpio::Pull::None, crate::private::Internal);
self.valid_pin.init_input(crate::gpio::Pull::None);
Instance::rx_valid_pin_signal().connect_to(&mut self.valid_pin);
Instance::set_rx_sw_en(false);
if let Some(sel) = self.enable_mode.pulse_submode_sel() {
@ -769,7 +765,7 @@ macro_rules! rx_pins {
{
fn configure(&mut self) -> Result<(), Error> {
$(
self.[< pin_ $pin:lower >].init_input(crate::gpio::Pull::None, crate::private::Internal);
self.[< pin_ $pin:lower >].init_input(crate::gpio::Pull::None);
crate::gpio::InputSignal::$signal.connect_to(&mut self.[< pin_ $pin:lower >]);
)+

4
esp-hal/src/pcnt/channel.rs
View File

@ -122,7 +122,7 @@ impl<const UNIT: usize, const NUM: usize> Channel<'_, UNIT, NUM> {
if (signal as usize) <= crate::gpio::INPUT_SIGNAL_MAX as usize {
crate::into_mapped_ref!(source);
source.enable_input(true, crate::private::Internal);
source.enable_input(true);
signal.connect_to(source);
}
self
@ -180,7 +180,7 @@ impl<const UNIT: usize, const NUM: usize> Channel<'_, UNIT, NUM> {
if (signal as usize) <= crate::gpio::INPUT_SIGNAL_MAX as usize {
crate::into_mapped_ref!(source);
source.enable_input(true, crate::private::Internal);
source.enable_input(true);
signal.connect_to(source);
}
self

3
esp-hal/src/peripheral.rs
View File

@ -419,15 +419,18 @@ mod peripheral_macros {
impl $name {
#[doc = r"Pointer to the register block"]
#[instability::unstable]
pub const PTR: *const <super::pac::$base as core::ops::Deref>::Target = super::pac::$base::PTR;
#[doc = r"Return the pointer to the register block"]
#[inline(always)]
#[instability::unstable]
pub const fn ptr() -> *const <super::pac::$base as core::ops::Deref>::Target {
super::pac::$base::PTR
}
}
#[doc(hidden)]
impl core::ops::Deref for $name {
type Target = <super::pac::$base as core::ops::Deref>::Target;

4
esp-hal/src/rmt.rs
View File

@ -445,7 +445,7 @@ fn configure_rx_channel<'d, P: PeripheralInput, T: RxChannelInternal<Dm>, Dm: cr
}
crate::into_mapped_ref!(pin);
pin.init_input(crate::gpio::Pull::None, crate::private::Internal);
pin.init_input(crate::gpio::Pull::None);
T::input_signal().connect_to(pin);
T::set_divider(config.clk_divider);
@ -471,7 +471,7 @@ fn configure_tx_channel<
config: TxChannelConfig,
) -> Result<T, Error> {
crate::into_mapped_ref!(pin);
pin.set_to_push_pull_output(crate::private::Internal);
pin.set_to_push_pull_output();
T::output_signal().connect_to(pin);
T::set_divider(config.clk_divider);

2
esp-hal/src/soc/esp32/gpio.rs
View File

@ -61,7 +61,7 @@ pub(crate) const INPUT_SIGNAL_MAX: u16 = 539;
pub(crate) const ONE_INPUT: u8 = 0x38;
pub(crate) const ZERO_INPUT: u8 = 0x30;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function2;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_2;
pub(crate) fn io_mux_reg(gpio_num: u8) -> &'static io_mux::GPIO0 {
unsafe {

2
esp-hal/src/soc/esp32c2/gpio.rs
View File

@ -52,7 +52,7 @@ pub(crate) const INPUT_SIGNAL_MAX: u8 = 100;
pub(crate) const ONE_INPUT: u8 = 0x1e;
pub(crate) const ZERO_INPUT: u8 = 0x1f;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_1;
pub(crate) const fn io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }

2
esp-hal/src/soc/esp32c3/gpio.rs
View File

@ -54,7 +54,7 @@ pub(crate) const INPUT_SIGNAL_MAX: u8 = 100;
pub(crate) const ONE_INPUT: u8 = 0x1e;
pub(crate) const ZERO_INPUT: u8 = 0x1f;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_1;
pub(crate) const fn io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }

2
esp-hal/src/soc/esp32c6/gpio.rs
View File

@ -54,7 +54,7 @@ pub(crate) const INPUT_SIGNAL_MAX: u8 = 124;
pub(crate) const ONE_INPUT: u8 = 0x38;
pub(crate) const ZERO_INPUT: u8 = 0x3c;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_1;
pub(crate) const fn io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }

2
esp-hal/src/soc/esp32h2/gpio.rs
View File

@ -52,7 +52,7 @@ pub(crate) const INPUT_SIGNAL_MAX: u8 = 124;
pub(crate) const ONE_INPUT: u8 = 0x38;
pub(crate) const ZERO_INPUT: u8 = 0x3c;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_1;
pub(crate) const fn io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }

2
esp-hal/src/soc/esp32s2/gpio.rs
View File

@ -67,7 +67,7 @@ pub(crate) const INPUT_SIGNAL_MAX: u16 = 204;
pub(crate) const ONE_INPUT: u8 = 0x38;
pub(crate) const ZERO_INPUT: u8 = 0x3c;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_1;
pub(crate) const fn io_mux_reg(gpio_num: u8) -> &'static io_mux::GPIO0 {
unsafe {

2
esp-hal/src/soc/esp32s3/gpio.rs
View File

@ -54,7 +54,7 @@ pub(crate) const INPUT_SIGNAL_MAX: u16 = 189;
pub(crate) const ONE_INPUT: u8 = 0x38;
pub(crate) const ZERO_INPUT: u8 = 0x3c;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::Function1;
pub(crate) const GPIO_FUNCTION: AlternateFunction = AlternateFunction::_1;
pub(crate) const fn io_mux_reg(gpio_num: u8) -> &'static crate::peripherals::io_mux::GPIO {
unsafe { (*crate::peripherals::IO_MUX::PTR).gpio(gpio_num as usize) }

22
esp-hal/src/spi/master.rs
View File

@ -643,8 +643,8 @@ where
/// to the MOSI signal and SIO0 input signal.
pub fn with_mosi<MOSI: PeripheralOutput>(self, mosi: impl Peripheral<P = MOSI> + 'd) -> Self {
crate::into_mapped_ref!(mosi);
mosi.enable_output(true, private::Internal);
mosi.enable_input(true, private::Internal);
mosi.enable_output(true);
mosi.enable_input(true);
self.driver().info.mosi.connect_to(&mut mosi);
self.driver().info.sio0_input.connect_to(&mut mosi);
@ -658,7 +658,7 @@ where
/// signal.
pub fn with_miso<MISO: PeripheralInput>(self, miso: impl Peripheral<P = MISO> + 'd) -> Self {
crate::into_mapped_ref!(miso);
miso.enable_input(true, private::Internal);
miso.enable_input(true);
self.driver().info.miso.connect_to(&mut miso);
@ -673,8 +673,8 @@ where
/// Note: You do not need to call [Self::with_miso] when this is used.
pub fn with_sio1<SIO1: PeripheralOutput>(self, miso: impl Peripheral<P = SIO1> + 'd) -> Self {
crate::into_mapped_ref!(miso);
miso.enable_input(true, private::Internal);
miso.enable_output(true, private::Internal);
miso.enable_input(true);
miso.enable_output(true);
self.driver().info.miso.connect_to(&mut miso);
self.driver().info.sio1_output.connect_to(&mut miso);
@ -688,7 +688,7 @@ where
/// clock signal.
pub fn with_sck<SCK: PeripheralOutput>(self, sclk: impl Peripheral<P = SCK> + 'd) -> Self {
crate::into_mapped_ref!(sclk);
sclk.set_to_push_pull_output(private::Internal);
sclk.set_to_push_pull_output();
self.driver().info.sclk.connect_to(sclk);
self
@ -706,7 +706,7 @@ where
#[instability::unstable]
pub fn with_cs<CS: PeripheralOutput>(self, cs: impl Peripheral<P = CS> + 'd) -> Self {
crate::into_mapped_ref!(cs);
cs.set_to_push_pull_output(private::Internal);
cs.set_to_push_pull_output();
self.driver().info.cs.connect_to(cs);
self
@ -748,8 +748,8 @@ where
pub fn with_sio2<SIO2: PeripheralOutput>(self, sio2: impl Peripheral<P = SIO2> + 'd) -> Self {
// TODO: panic if not QSPI?
crate::into_mapped_ref!(sio2);
sio2.enable_input(true, private::Internal);
sio2.enable_output(true, private::Internal);
sio2.enable_input(true);
sio2.enable_output(true);
unwrap!(self.driver().info.sio2_input).connect_to(&mut sio2);
unwrap!(self.driver().info.sio2_output).connect_to(&mut sio2);
@ -769,8 +769,8 @@ where
pub fn with_sio3<SIO3: PeripheralOutput>(self, sio3: impl Peripheral<P = SIO3> + 'd) -> Self {
// TODO: panic if not QSPI?
crate::into_mapped_ref!(sio3);
sio3.enable_input(true, private::Internal);
sio3.enable_output(true, private::Internal);
sio3.enable_input(true);
sio3.enable_output(true);
unwrap!(self.driver().info.sio3_input).connect_to(&mut sio3);
unwrap!(self.driver().info.sio3_output).connect_to(&mut sio3);

9
esp-hal/src/spi/slave.rs
View File

@ -82,7 +82,6 @@ use crate::{
},
peripheral::{Peripheral, PeripheralRef},
peripherals::spi2::RegisterBlock,
private,
spi::AnySpi,
system::PeripheralGuard,
Blocking,
@ -129,7 +128,7 @@ impl<'d> Spi<'d, Blocking> {
#[instability::unstable]
pub fn with_sck(self, sclk: impl Peripheral<P = impl PeripheralInput> + 'd) -> Self {
crate::into_mapped_ref!(sclk);
sclk.enable_input(true, private::Internal);
sclk.enable_input(true);
self.spi.info().sclk.connect_to(sclk);
self
}
@ -138,7 +137,7 @@ impl<'d> Spi<'d, Blocking> {
#[instability::unstable]
pub fn with_mosi(self, mosi: impl Peripheral<P = impl PeripheralInput> + 'd) -> Self {
crate::into_mapped_ref!(mosi);
mosi.enable_input(true, private::Internal);
mosi.enable_input(true);
self.spi.info().mosi.connect_to(mosi);
self
}
@ -147,7 +146,7 @@ impl<'d> Spi<'d, Blocking> {
#[instability::unstable]
pub fn with_miso(self, miso: impl Peripheral<P = impl PeripheralOutput> + 'd) -> Self {
crate::into_mapped_ref!(miso);
miso.set_to_push_pull_output(private::Internal);
miso.set_to_push_pull_output();
self.spi.info().miso.connect_to(miso);
self
}
@ -156,7 +155,7 @@ impl<'d> Spi<'d, Blocking> {
#[instability::unstable]
pub fn with_cs(self, cs: impl Peripheral<P = impl PeripheralInput> + 'd) -> Self {
crate::into_mapped_ref!(cs);
cs.enable_input(true, private::Internal);
cs.enable_input(true);
self.spi.info().cs.connect_to(cs);
self
}

8
esp-hal/src/twai/mod.rs
View File

@ -717,11 +717,11 @@ where
// Set up the GPIO pins.
let rx_pull = if no_transceiver {
tx_pin.set_to_open_drain_output(crate::private::Internal);
tx_pin.pull_direction(Pull::Up, crate::private::Internal);
tx_pin.set_to_open_drain_output();
tx_pin.pull_direction(Pull::Up);
Pull::Up
} else {
tx_pin.set_to_push_pull_output(crate::private::Internal);
tx_pin.set_to_push_pull_output();
Pull::None
};
this.twai.output_signal().connect_to(tx_pin);
@ -729,7 +729,7 @@ where
// Setting up RX pin later allows us to use a single pin in tests.
// `set_to_push_pull_output` disables input, here we re-enable it if rx_pin
// uses the same GPIO.
rx_pin.init_input(rx_pull, crate::private::Internal);
rx_pin.init_input(rx_pull);
this.twai.input_signal().connect_to(rx_pin);
// Freeze REC by changing to LOM mode

17
esp-hal/src/uart.rs
View File

@ -241,7 +241,6 @@ use crate::{
interrupt::{InterruptConfigurable, InterruptHandler},
peripheral::{Peripheral, PeripheralRef},
peripherals::{uart0::RegisterBlock, Interrupt},
private::Internal,
system::{PeripheralClockControl, PeripheralGuard},
Async,
Blocking,
@ -613,7 +612,7 @@ where
/// Configure RTS pin
pub fn with_rts(self, rts: impl Peripheral<P = impl PeripheralOutput> + 'd) -> Self {
crate::into_mapped_ref!(rts);
rts.set_to_push_pull_output(Internal);
rts.set_to_push_pull_output();
self.uart.info().rts_signal.connect_to(rts);
self
@ -626,8 +625,8 @@ where
pub fn with_tx(self, tx: impl Peripheral<P = impl PeripheralOutput> + 'd) -> Self {
crate::into_mapped_ref!(tx);
// Make sure we don't cause an unexpected low pulse on the pin.
tx.set_output_high(true, Internal);
tx.set_to_push_pull_output(Internal);
tx.set_output_high(true);
tx.set_to_push_pull_output();
self.uart.info().tx_signal.connect_to(tx);
self
@ -796,7 +795,7 @@ where
/// Configure CTS pin
pub fn with_cts(self, cts: impl Peripheral<P = impl PeripheralInput> + 'd) -> Self {
crate::into_mapped_ref!(cts);
cts.init_input(Pull::None, Internal);
cts.init_input(Pull::None);
self.uart.info().cts_signal.connect_to(cts);
self
@ -812,7 +811,7 @@ where
/// initial low signal level.
pub fn with_rx(self, rx: impl Peripheral<P = impl PeripheralInput> + 'd) -> Self {
crate::into_mapped_ref!(rx);
rx.init_input(Pull::Up, Internal);
rx.init_input(Pull::Up);
self.uart.info().rx_signal.connect_to(rx);
self
@ -1004,7 +1003,7 @@ impl<'d> Uart<'d, Blocking> {
/// initial low signal level.
pub fn with_rx(self, rx: impl Peripheral<P = impl PeripheralInput> + 'd) -> Self {
crate::into_mapped_ref!(rx);
rx.init_input(Pull::Up, Internal);
rx.init_input(Pull::Up);
self.rx.uart.info().rx_signal.connect_to(rx);
self
@ -1017,8 +1016,8 @@ impl<'d> Uart<'d, Blocking> {
pub fn with_tx(self, tx: impl Peripheral<P = impl PeripheralOutput> + 'd) -> Self {
crate::into_mapped_ref!(tx);
// Make sure we don't cause an unexpected low pulse on the pin.
tx.set_output_high(true, Internal);
tx.set_to_push_pull_output(Internal);
tx.set_output_high(true);
tx.set_to_push_pull_output();
self.tx.uart.info().tx_signal.connect_to(tx);
self

10
hil-test/tests/uart_regression.rs
View File

@ -10,7 +10,7 @@
#[embedded_test::tests(default_timeout = 3)]
mod tests {
use esp_hal::{
gpio::OutputPin,
gpio::Flex,
uart::{self, UartRx, UartTx},
};
use hil_test as _;
@ -19,7 +19,7 @@ mod tests {
fn test_that_creating_tx_does_not_cause_a_pulse() {
let peripherals = esp_hal::init(esp_hal::Config::default());
let (rx, mut tx) = hil_test::common_test_pins!(peripherals);
let (rx, tx) = hil_test::common_test_pins!(peripherals);
let mut rx = UartRx::new(peripherals.UART1, uart::Config::default())
.unwrap()
@ -29,7 +29,11 @@ mod tests {
let mut buf = [0u8; 1];
_ = rx.read_bytes(&mut buf); // this will just return WouldBlock
unsafe { tx.set_output_high(false, esp_hal::Internal::conjure()) };
// Start from a low level to verify that UartTx sets the level high initially,
// but don't enable output otherwise we actually pull down against RX's
// pullup resistor.
let mut tx = Flex::new(tx);
tx.set_low();
// set up TX and send a byte
let mut tx = UartTx::new(peripherals.UART0, uart::Config::default())