mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-02 14:44:42 +00:00
rmt: don't use the paste! macro (#2976)
There's no need for it, the PACs have accessor methods that take channel indices (which were already used in a few places).
This commit is contained in:
Benedikt
GitHub
parent
3fac1979d0
commit
e150a537fc
@ -1761,7 +1761,6 @@ mod chip_specific {
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macro_rules! impl_tx_channel {
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($signal:ident, $ch_num:literal) => {
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paste::paste! {
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impl<Dm> $crate::rmt::TxChannelInternal<Dm> for $crate::rmt::Channel<Dm, $ch_num> where Dm: $crate::DriverMode {
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const CHANNEL: u8 = $ch_num;
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@ -1810,10 +1809,10 @@ mod chip_specific {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_clr().write(|w| {
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w.[< ch $ch_num _tx_end >]().set_bit();
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w.[< ch $ch_num _tx_err >]().set_bit();
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w.[< ch $ch_num _tx_loop >]().set_bit();
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w.[< ch $ch_num _tx_thr_event >]().set_bit()
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w.ch_tx_end($ch_num).set_bit();
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w.ch_tx_err($ch_num).set_bit();
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w.ch_tx_loop($ch_num).set_bit();
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w.ch_tx_thr_event($ch_num).set_bit()
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});
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}
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@ -1869,23 +1868,23 @@ mod chip_specific {
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fn is_done() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _tx_end >]().bit()
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rmt.int_raw().read().ch_tx_end($ch_num).bit()
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}
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fn is_error() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _tx_err >]().bit()
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rmt.int_raw().read().ch_tx_err($ch_num).bit()
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}
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fn is_threshold_set() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _tx_thr_event >]().bit()
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rmt.int_raw().read().ch_tx_thr_event($ch_num).bit()
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}
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fn reset_threshold_set() {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_clr()
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.write(|w| w.[< ch $ch_num _tx_thr_event >]().set_bit());
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.write(|w| w.ch_tx_thr_event($ch_num).set_bit());
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}
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fn set_threshold(threshold: u8) {
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@ -1895,7 +1894,7 @@ mod chip_specific {
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fn is_loopcount_interrupt_set() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _tx_loop >]().bit()
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rmt.int_raw().read().ch_tx_loop($ch_num).bit()
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}
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fn stop() {
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@ -1908,13 +1907,13 @@ mod chip_specific {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_ena().modify(|_, w| {
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if events.contains($crate::rmt::Event::Error) {
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w.[< ch $ch_num _tx_err >]().bit(enable);
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w.ch_tx_err($ch_num).bit(enable);
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}
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if events.contains($crate::rmt::Event::End) {
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w.[< ch $ch_num _tx_end >]().bit(enable);
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w.ch_tx_end($ch_num).bit(enable);
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}
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if events.contains($crate::rmt::Event::Threshold) {
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w.[< ch $ch_num _tx_thr_event >]().bit(enable);
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w.ch_tx_thr_event($ch_num).bit(enable);
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}
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w
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});
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@ -1922,11 +1921,9 @@ mod chip_specific {
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}
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}
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}
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}
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macro_rules! impl_rx_channel {
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($signal:ident, $ch_num:literal, $ch_index:literal) => {
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paste::paste! {
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impl<Dm> $crate::rmt::RxChannelInternal<Dm> for $crate::rmt::Channel<Dm, $ch_num> where Dm: $crate::DriverMode {
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const CHANNEL: u8 = $ch_num;
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@ -1944,27 +1941,27 @@ mod chip_specific {
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fn set_divider(divider: u8) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| unsafe { w.div_cnt().bits(divider) });
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rmt.ch_rx_conf0($ch_index).modify(|_, w| unsafe { w.div_cnt().bits(divider) });
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}
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fn update() {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| w.conf_update().set_bit());
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rmt.ch_rx_conf1($ch_index).modify(|_, w| w.conf_update().set_bit());
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}
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fn clear_interrupts() {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_clr().write(|w| {
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w.[< ch $ch_num _rx_end >]().set_bit();
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w.[< ch $ch_num _rx_err >]().set_bit();
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w.[< ch $ch_num _rx_thr_event >]().set_bit()
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w.ch_rx_end($ch_index).set_bit();
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w.ch_rx_err($ch_index).set_bit();
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w.ch_rx_thr_event($ch_index).set_bit()
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});
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}
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fn set_wrap_mode(wrap: bool) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| w.mem_rx_wrap_en().bit(wrap));
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rmt.ch_rx_conf1($ch_index).modify(|_, w| w.mem_rx_wrap_en().bit(wrap));
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}
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fn set_carrier(carrier: bool, high: u16, low: u16, level: bool) {
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@ -1975,18 +1972,18 @@ mod chip_specific {
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w.carrier_low_thres().bits(low)
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});
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rmt.[< ch $ch_num _rx_conf0 >]()
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rmt.ch_rx_conf0($ch_index)
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.modify(|_, w| w.carrier_en().bit(carrier).carrier_out_lv().bit(level));
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}
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fn set_memsize(memsize: u8) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| unsafe { w.mem_size().bits(memsize) });
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rmt.ch_rx_conf0($ch_index).modify(|_, w| unsafe { w.mem_size().bits(memsize) });
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}
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fn start_rx() {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| {
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rmt.ch_rx_conf1($ch_index).modify(|_, w| {
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w.mem_wr_rst().set_bit();
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w.apb_mem_rst().set_bit();
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w.mem_owner().set_bit();
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@ -1996,23 +1993,23 @@ mod chip_specific {
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fn is_done() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _rx_end >]().bit()
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rmt.int_raw().read().ch_rx_end($ch_index).bit()
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}
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fn is_error() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _rx_err >]().bit()
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rmt.int_raw().read().ch_rx_err($ch_index).bit()
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}
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fn stop() {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| w.rx_en().clear_bit());
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rmt.ch_rx_conf1($ch_index).modify(|_, w| w.rx_en().clear_bit());
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}
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fn set_filter_threshold(value: u8) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num _rx_conf1 >]().modify(|_, w| unsafe {
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rmt.ch_rx_conf1($ch_index).modify(|_, w| unsafe {
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w.rx_filter_en().bit(value > 0);
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w.rx_filter_thres().bits(value)
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});
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@ -2021,20 +2018,20 @@ mod chip_specific {
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fn set_idle_threshold(value: u16) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num _rx_conf0 >]().modify(|_, w| unsafe { w.idle_thres().bits(value) });
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rmt.ch_rx_conf0($ch_index).modify(|_, w| unsafe { w.idle_thres().bits(value) });
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}
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fn enable_listen_interrupt(events: enumset::EnumSet<$crate::rmt::Event>, enable: bool) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_ena().modify(|_, w| {
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if events.contains($crate::rmt::Event::Error) {
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w.[< ch $ch_num _rx_err >]().bit(enable);
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w.ch_rx_err($ch_index).bit(enable);
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}
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if events.contains($crate::rmt::Event::End) {
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w.[< ch $ch_num _rx_end >]().bit(enable);
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w.ch_rx_end($ch_index).bit(enable);
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}
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if events.contains($crate::rmt::Event::Threshold) {
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w.[< ch $ch_num _rx_thr_event >]().bit(enable);
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w.ch_rx_thr_event($ch_index).bit(enable);
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}
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w
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});
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@ -2042,7 +2039,6 @@ mod chip_specific {
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}
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}
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}
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}
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pub(crate) use impl_rx_channel;
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pub(crate) use impl_tx_channel;
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@ -2119,7 +2115,6 @@ mod chip_specific {
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macro_rules! impl_tx_channel {
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($signal:ident, $ch_num:literal) => {
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paste::paste! {
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impl<Dm> super::TxChannelInternal<Dm> for $crate::rmt::Channel<Dm, $ch_num> where Dm: $crate::DriverMode {
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const CHANNEL: u8 = $ch_num;
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@ -2137,7 +2132,7 @@ mod chip_specific {
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fn set_divider(divider: u8) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.div_cnt().bits(divider) });
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rmt.chconf0($ch_num).modify(|_, w| unsafe { w.div_cnt().bits(divider) });
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}
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fn update() {
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@ -2163,16 +2158,16 @@ mod chip_specific {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_clr().write(|w| {
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w.[< ch $ch_num _err >]().set_bit();
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w.[< ch $ch_num _tx_end >]().set_bit();
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w.[< ch $ch_num _tx_thr_event >]().set_bit()
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w.ch_err($ch_num).set_bit();
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w.ch_tx_end($ch_num).set_bit();
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w.ch_tx_thr_event($ch_num).set_bit()
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});
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}
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fn set_continuous(continuous: bool) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num conf1 >]().modify(|_, w| w.tx_conti_mode().bit(continuous));
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rmt.chconf1($ch_num).modify(|_, w| w.tx_conti_mode().bit(continuous));
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}
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fn set_wrap_mode(wrap: bool) {
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@ -2187,26 +2182,26 @@ mod chip_specific {
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rmt.chcarrier_duty($ch_num)
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.write(|w| unsafe { w.carrier_high().bits(high).carrier_low().bits(low) });
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rmt.[< ch $ch_num conf0 >]()
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rmt.chconf0($ch_num)
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.modify(|_, w| w.carrier_en().bit(carrier).carrier_out_lv().bit(level));
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}
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fn set_idle_output(enable: bool, level: bool) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num conf1 >]()
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rmt.chconf1($ch_num)
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.modify(|_, w| w.idle_out_en().bit(enable).idle_out_lv().bit(level));
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}
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fn set_memsize(memsize: u8) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.mem_size().bits(memsize) });
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rmt.chconf0($ch_num).modify(|_, w| unsafe { w.mem_size().bits(memsize) });
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}
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fn start_tx() {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num conf1 >]().modify(|_, w| {
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rmt.chconf1($ch_num).modify(|_, w| {
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w.mem_rd_rst().set_bit();
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w.apb_mem_rst().set_bit();
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w.tx_start().set_bit()
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@ -2215,23 +2210,23 @@ mod chip_specific {
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fn is_done() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _tx_end >]().bit()
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rmt.int_raw().read().ch_tx_end($ch_num).bit()
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}
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fn is_error() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _err >]().bit()
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rmt.int_raw().read().ch_err($ch_num).bit()
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}
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fn is_threshold_set() -> bool {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_raw().read().[< ch $ch_num _tx_thr_event >]().bit()
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rmt.int_raw().read().ch_tx_thr_event($ch_num).bit()
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}
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fn reset_threshold_set() {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_clr()
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.write(|w| w.[< ch $ch_num _tx_thr_event >]().set_bit());
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.write(|w| w.ch_tx_thr_event($ch_num).set_bit());
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}
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fn set_threshold(threshold: u8) {
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@ -2248,7 +2243,7 @@ mod chip_specific {
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#[cfg(esp32s2)]
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{
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num conf1 >]().modify(|_, w| w.tx_stop().set_bit());
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rmt.chconf1($ch_num).modify(|_, w| w.tx_stop().set_bit());
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}
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}
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@ -2256,13 +2251,13 @@ mod chip_specific {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.int_ena().modify(|_,w| {
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if events.contains($crate::rmt::Event::Error) {
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w.[< ch $ch_num _err >]().bit(enable);
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w.ch_err($ch_num).bit(enable);
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}
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if events.contains($crate::rmt::Event::End) {
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w.[< ch $ch_num _tx_end >]().bit(enable);
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w.ch_tx_end($ch_num).bit(enable);
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}
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if events.contains($crate::rmt::Event::Threshold) {
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w.[< ch $ch_num _tx_thr_event >]().bit(enable);
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w.ch_tx_thr_event($ch_num).bit(enable);
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}
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w
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});
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@ -2270,11 +2265,9 @@ mod chip_specific {
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}
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}
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}
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}
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macro_rules! impl_rx_channel {
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($signal:ident, $ch_num:literal) => {
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paste::paste! {
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impl<Dm> super::RxChannelInternal<Dm> for $crate::rmt::Channel<Dm, $ch_num> where Dm: $crate::DriverMode {
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const CHANNEL: u8 = $ch_num;
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@ -2292,7 +2285,7 @@ mod chip_specific {
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fn set_divider(divider: u8) {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.div_cnt().bits(divider) });
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rmt.chconf0($ch_num).modify(|_, w| unsafe { w.div_cnt().bits(divider) });
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}
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fn update() {
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@ -2302,7 +2295,7 @@ mod chip_specific {
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fn clear_interrupts() {
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let rmt = unsafe { &*crate::peripherals::RMT::PTR };
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rmt.[< ch $ch_num conf1 >]().modify(|_, w| {
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rmt.chconf1($ch_num).modify(|_, w| {
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w.mem_wr_rst().set_bit();
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w.apb_mem_rst().set_bit();
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w.mem_owner().set_bit();
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@ -2311,9 +2304,9 @@ mod chip_specific {
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Self::update();
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rmt.int_clr().write(|w| {
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w.[< ch $ch_num _rx_end >]().set_bit();
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w.[< ch $ch_num _err >]().set_bit();
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w.[< ch $ch_num _tx_thr_event >]().set_bit()
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w.ch_rx_end($ch_num).set_bit();
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w.ch_err($ch_num).set_bit();
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w.ch_tx_thr_event($ch_num).set_bit()
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});
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}
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@ -2327,20 +2320,20 @@ mod chip_specific {
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rmt.chcarrier_duty($ch_num)
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.write(|w| unsafe { w.carrier_high().bits(high).carrier_low().bits(low) });
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rmt.[< ch $ch_num conf0 >]()
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rmt.chconf0($ch_num)
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.modify(|_, w| w.carrier_en().bit(carrier).carrier_out_lv().bit(level));
|
||||
}
|
||||
|
||||
fn set_memsize(memsize: u8) {
|
||||
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
|
||||
|
||||
rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.mem_size().bits(memsize) });
|
||||
rmt.chconf0($ch_num).modify(|_, w| unsafe { w.mem_size().bits(memsize) });
|
||||
}
|
||||
|
||||
fn start_rx() {
|
||||
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
|
||||
|
||||
rmt.[< ch $ch_num conf1 >]().modify(|_, w| {
|
||||
rmt.chconf1($ch_num).modify(|_, w| {
|
||||
w.mem_wr_rst().set_bit();
|
||||
w.apb_mem_rst().set_bit();
|
||||
w.mem_owner().set_bit();
|
||||
@ -2350,22 +2343,22 @@ mod chip_specific {
|
||||
|
||||
fn is_done() -> bool {
|
||||
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
|
||||
rmt.int_raw().read().[< ch $ch_num _rx_end >]().bit()
|
||||
rmt.int_raw().read().ch_rx_end($ch_num).bit()
|
||||
}
|
||||
|
||||
fn is_error() -> bool {
|
||||
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
|
||||
rmt.int_raw().read().[< ch $ch_num _err >]().bit()
|
||||
rmt.int_raw().read().ch_err($ch_num).bit()
|
||||
}
|
||||
|
||||
fn stop() {
|
||||
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
|
||||
rmt.[< ch $ch_num conf1 >]().modify(|_, w| w.rx_en().clear_bit());
|
||||
rmt.chconf1($ch_num).modify(|_, w| w.rx_en().clear_bit());
|
||||
}
|
||||
|
||||
fn set_filter_threshold(value: u8) {
|
||||
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
|
||||
rmt.[< ch $ch_num conf1 >]().modify(|_, w| unsafe {
|
||||
rmt.chconf1($ch_num).modify(|_, w| unsafe {
|
||||
w.rx_filter_en().bit(value > 0);
|
||||
w.rx_filter_thres().bits(value)
|
||||
});
|
||||
@ -2374,20 +2367,20 @@ mod chip_specific {
|
||||
fn set_idle_threshold(value: u16) {
|
||||
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
|
||||
|
||||
rmt.[< ch $ch_num conf0 >]().modify(|_, w| unsafe { w.idle_thres().bits(value) });
|
||||
rmt.chconf0($ch_num).modify(|_, w| unsafe { w.idle_thres().bits(value) });
|
||||
}
|
||||
|
||||
fn enable_listen_interrupt(events: enumset::EnumSet<$crate::rmt::Event>, enable: bool) {
|
||||
let rmt = unsafe { &*crate::peripherals::RMT::PTR };
|
||||
rmt.int_ena().modify(|_, w| {
|
||||
if events.contains($crate::rmt::Event::Error) {
|
||||
w.[< ch $ch_num _err >]().bit(enable);
|
||||
w.ch_err($ch_num).bit(enable);
|
||||
}
|
||||
if events.contains($crate::rmt::Event::End) {
|
||||
w.[< ch $ch_num _rx_end >]().bit(enable);
|
||||
w.ch_rx_end($ch_num).bit(enable);
|
||||
}
|
||||
if events.contains($crate::rmt::Event::Threshold) {
|
||||
w.[< ch $ch_num _tx_thr_event >]().bit(enable);
|
||||
w.ch_tx_thr_event($ch_num).bit(enable);
|
||||
}
|
||||
w
|
||||
});
|
||||
@ -2395,7 +2388,6 @@ mod chip_specific {
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) use impl_rx_channel;
|
||||
pub(crate) use impl_tx_channel;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user