Depend on the published riscv-rt

esp32c3-hal/Cargo.toml

@@ -31,6 +31,7 @@ bare-metal   = "1.0"
 embedded-hal = { version = "0.2", features = ["unproven"] }
 nb           = "1.0"
 riscv        = "0.7"
+riscv-rt     = { version = "0.8.1", optional = true }
 void         = { version = "1.0", default-features = false }
 r0           = "1.0.0"
 
@@ -38,11 +39,6 @@ r0           = "1.0.0"
 path     = "../esp-hal-common"
 features = ["esp32c3"]
 
-[dependencies.riscv-rt] 
-git      = "https://github.com/MabezDev/riscv-rt"
-rev      = "6b55e4aa3895924e31bcd151f2f0ab840836fa07"
-optional = true
-
 [build-dependencies]
 riscv-target = "0.1.2"
 

esp32c3-hal/asm.S

@@ -3,6 +3,99 @@
 #define LOG_REGBYTES 2
 #define REGBYTES (1 << LOG_REGBYTES)
 
+
+/*
+    Entry point of all programs (_start).
+    It initializes DWARF call frame information, the stack pointer, the
+    frame pointer (needed for closures to work in start_rust) and the global
+    pointer. Then it calls _start_rust.
+*/
+
+.section .init, "ax"
+.global _start
+
+_start_hal:
+    /* Jump to the absolute address defined by the linker script. */
+    lui ra, %hi(_abs_start_hal)
+    jr %lo(_abs_start_hal)(ra)
+
+_abs_start_hal:
+    .cfi_startproc
+    .cfi_undefined ra
+
+    // unsupported on ESP32C3
+    // csrw mie, 0
+    // csrw mip, 0
+
+    li  x1, 0
+    li  x2, 0
+    li  x3, 0
+    li  x4, 0
+    li  x5, 0
+    li  x6, 0
+    li  x7, 0
+    li  x8, 0
+    li  x9, 0
+    li  x10,0
+    li  x11,0
+    li  x12,0
+    li  x13,0
+    li  x14,0
+    li  x15,0
+    li  x16,0
+    li  x17,0
+    li  x18,0
+    li  x19,0
+    li  x20,0
+    li  x21,0
+    li  x22,0
+    li  x23,0
+    li  x24,0
+    li  x25,0
+    li  x26,0
+    li  x27,0
+    li  x28,0
+    li  x29,0
+    li  x30,0
+    li  x31,0
+
+    .option push
+    .option norelax
+    la gp, __global_pointer$
+    .option pop
+
+    // Check hart id
+    csrr a2, mhartid
+    lui t0, %hi(_max_hart_id)
+    add t0, t0, %lo(_max_hart_id)
+    bgtu a2, t0, abort
+
+    // Allocate stacks
+    la sp, _stack_start
+    lui t0, %hi(_hart_stack_size)
+    add t0, t0, %lo(_hart_stack_size)
+#ifdef __riscv_mul
+    mul t0, a2, t0
+#else
+    beqz a2, 2f  // Jump if single-hart
+    mv t1, a2
+    mv t2, t0
+1:
+    add t0, t0, t2
+    addi t1, t1, -1
+    bnez t1, 1b
+2:
+#endif
+    sub sp, sp, t0
+
+    // Set frame pointer
+    add s0, sp, zero
+
+    jal zero, _start_rust
+
+    .cfi_endproc
+
+
 /*
     Trap entry point (_start_trap)
     Saves registers and calls _start_trap_rust_hal,

esp32c3-hal/ld/bl-riscv-link.x

@@ -1,3 +1,6 @@
+ENTRY(_start_hal)
+PROVIDE(_start_trap = _start_trap_hal);
+
 PROVIDE(_stext = ORIGIN(REGION_TEXT));
 PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
 PROVIDE(_max_hart_id = 0);

esp32c3-hal/ld/db-riscv-link.x

@@ -1,3 +1,6 @@
+ENTRY(_start_hal)
+PROVIDE(_start_trap = _start_trap_hal);
+
 PROVIDE(_stext = ORIGIN(REGION_TEXT));
 PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
 PROVIDE(_max_hart_id = 0);