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https://github.com/esp-rs/esp-hal.git
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Do not reset UsbSerialJtag
peripheral (#1961)
* Fix typos * Add a function to detect debugger connection * Do not reset USB peripheral * Changelog * Fix different register names * Reuse xtensa_lx::is_debugger_attached
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@ -13,7 +13,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- Added touch pad support for esp32 (#1873, #1956)
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- Allow configuration of period updating method for MCPWM timers (#1898)
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- Add self-testing mode for TWAI peripheral. (#1929)
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- Added a `PeripheralClockControl::reset` to the driver constructors where missing (#1893)
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- Added `debugger::debugger_connected`. (#1961)
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### Changed
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@ -23,6 +23,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
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- Allow DMA to/from psram for esp32s3 (#1827)
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- DMA buffers now don't require a static lifetime. Make sure to never `mem::forget` an in-progress DMA transfer (consider using `#[deny(clippy::mem_forget)]`) (#1837)
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- Peripherals (where possible) are now explicitly reset and enabled in their constructors (#1893)
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- Reset peripherals in driver constructors where missing (#1893, #1961)
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### Fixed
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@ -68,7 +68,7 @@ impl<'d> InterruptConfigurable for DebugAssist<'d> {
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#[cfg(assist_debug_sp_monitor)]
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impl<'d> DebugAssist<'d> {
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/// Enable SP monitoring on main core. When the SP exceeds the
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/// `lower_bound` or `upper_bound` treshold, the module will record the PC
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/// `lower_bound` or `upper_bound` threshold, the module will record the PC
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/// pointer and generate an interrupt.
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pub fn enable_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) {
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self.debug_assist
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@ -150,8 +150,8 @@ impl<'d> DebugAssist<'d> {
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#[cfg(all(assist_debug_sp_monitor, multi_core))]
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impl<'d> DebugAssist<'d> {
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/// Enable SP monitoring on secondondary core. When the SP exceeds the
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/// `lower_bound` or `upper_bound` treshold, the module will record the PC
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/// Enable SP monitoring on secondary core. When the SP exceeds the
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/// `lower_bound` or `upper_bound` threshold, the module will record the PC
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/// pointer and generate an interrupt.
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pub fn enable_core1_sp_monitor(&mut self, lower_bound: u32, upper_bound: u32) {
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self.debug_assist
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@ -384,7 +384,7 @@ impl<'d> DebugAssist<'d> {
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.bit_is_set()
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}
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/// Get region monotoring PC value on main core.
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/// Get region monitoring PC value on main core.
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pub fn get_region_monitor_pc(&self) -> u32 {
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self.debug_assist
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.core_0_area_pc()
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@ -550,7 +550,7 @@ impl<'d> DebugAssist<'d> {
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.bit_is_set()
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}
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/// Get region monotoring PC value on secondary core.
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/// Get region monitoring PC value on secondary core.
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pub fn get_core1_region_monitor_pc(&self) -> u32 {
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self.debug_assist
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.core_1_area_pc()
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36
esp-hal/src/debugger.rs
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36
esp-hal/src/debugger.rs
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@ -0,0 +1,36 @@
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//! Debugger utilities
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/// Checks if a debugger is connected.
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pub fn debugger_connected() -> bool {
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#[cfg(xtensa)]
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{
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xtensa_lx::is_debugger_attached()
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}
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#[cfg(riscv)]
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{
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use crate::peripherals::ASSIST_DEBUG;
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let assist_debug = unsafe { &*ASSIST_DEBUG::ptr() };
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#[cfg(feature = "esp32c2")]
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{
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assist_debug
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.core_0_debug_mode()
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.read()
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.core_0_debug_module_active()
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.bit_is_set()
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}
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#[cfg(not(feature = "esp32c2"))]
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{
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assist_debug
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.c0re_0_debug_mode()
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.read()
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.core_0_debug_module_active()
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.bit_is_set()
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}
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}
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#[cfg(not(any(xtensa, riscv)))]
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{
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false
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}
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}
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@ -241,6 +241,8 @@ pub mod uart;
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#[cfg(usb_device)]
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pub mod usb_serial_jtag;
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pub mod debugger;
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/// State of the CPU saved when entering exception or interrupt
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pub mod trapframe {
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#[cfg(riscv)]
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@ -273,7 +273,8 @@ where
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M: Mode,
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{
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fn new_inner(_usb_device: impl Peripheral<P = USB_DEVICE> + 'd) -> Self {
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PeripheralClockControl::reset(crate::system::Peripheral::UsbDevice);
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// Do NOT reset the peripheral. Doing so will result in a broken USB JTAG
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// connection.
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PeripheralClockControl::enable(crate::system::Peripheral::UsbDevice);
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USB_DEVICE::disable_tx_interrupts();
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@ -311,7 +312,7 @@ where
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}
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/// Split the USB Serial JTAG peripheral into a transmitter and receiver,
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/// which is particuarly useful when having two tasks correlating to
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/// which is particularly useful when having two tasks correlating to
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/// transmitting and receiving.
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pub fn split(self) -> (UsbSerialJtagTx<'d, M>, UsbSerialJtagRx<'d, M>) {
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(self.tx, self.rx)
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@ -100,6 +100,10 @@ harness = false
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name = "uart"
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harness = false
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[[test]]
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name = "usb_serial_jtag"
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harness = false
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[[test]]
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name = "uart_async"
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harness = false
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45
hil-test/tests/usb_serial_jtag.rs
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45
hil-test/tests/usb_serial_jtag.rs
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@ -0,0 +1,45 @@
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//! USB Serial JTAG tests
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//% CHIPS: esp32c3 esp32c6 esp32h2 esp32s3
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#![no_std]
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#![no_main]
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#[cfg(test)]
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#[embedded_test::tests]
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mod tests {
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use defmt_rtt as _;
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use esp_backtrace as _;
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use esp_hal::{
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clock::ClockControl,
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peripherals::Peripherals,
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system::SystemControl,
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timer::{timg::TimerGroup, ErasedTimer, OneShotTimer},
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usb_serial_jtag::UsbSerialJtag,
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};
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// When you are okay with using a nightly compiler it's better to use https://docs.rs/static_cell/2.1.0/static_cell/macro.make_static.html
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macro_rules! mk_static {
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($t:ty,$val:expr) => {{
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static STATIC_CELL: static_cell::StaticCell<$t> = static_cell::StaticCell::new();
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#[deny(unused_attributes)]
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let x = STATIC_CELL.uninit().write(($val));
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x
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}};
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}
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#[test]
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fn creating_peripheral_does_not_break_debug_connection() {
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let peripherals = Peripherals::take();
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let system = SystemControl::new(peripherals.SYSTEM);
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let timg0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let timer0: ErasedTimer = timg0.timer0.into();
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let timers = [OneShotTimer::new(timer0)];
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let timers = mk_static!([OneShotTimer<ErasedTimer>; 1], timers);
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esp_hal_embassy::init(&clocks, timers);
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_ = UsbSerialJtag::new_async(peripherals.USB_DEVICE).split();
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}
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}
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