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Riscv stable CI (#1491)

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* Remove interrupt and thread executor embassy features

* Reserve sw interrupt 3 (4) instead of 0 for multicore systems with the embassy feature enabled

* Add thread mode context id and fix up examples

* Use stable rust for riscv CI

* Add binary-logs feature to 8021504 driver

* Add binary-logs feature to 8021504 driver
This commit is contained in:
Scott Mabin 2024-05-22 17:36:39 +01:00 committed by GitHub
parent 76ed67ad35
commit ec8308058b
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GPG Key ID: B5690EEEBB952194
7 changed files with 159 additions and 137 deletions
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18
.github/workflows/ci.yml vendored
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@ -71,7 +71,7 @@ jobs:
uses: dtolnay/rust-toolchain@v1
with:
target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
toolchain: nightly
toolchain: stable
components: rust-src
# Install the Rust toolchain for Xtensa devices:
- if: contains(fromJson('["esp32", "esp32s2", "esp32s3"]'), matrix.device.soc)
@ -119,7 +119,7 @@ jobs:
- uses: dtolnay/rust-toolchain@v1
with:
target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf
toolchain: nightly
toolchain: stable
components: rust-src
- uses: Swatinem/rust-cache@v2
@ -139,24 +139,24 @@ jobs:
- uses: dtolnay/rust-toolchain@v1
with:
target: riscv32imc-unknown-none-elf,riscv32imac-unknown-none-elf,riscv32imafc-unknown-none-elf
toolchain: nightly
toolchain: stable
components: rust-src
- uses: Swatinem/rust-cache@v2
# Build for all RISC-V targets (no features):
- name: Build esp-riscv-rt (riscv32imc, no features)
run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imc-unknown-none-elf
run: cd esp-riscv-rt/ && cargo build --target=riscv32imc-unknown-none-elf
- name: Build esp-riscv-rt (riscv32imac, no features)
run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imac-unknown-none-elf
run: cd esp-riscv-rt/ && cargo build --target=riscv32imac-unknown-none-elf
- name: Build esp-riscv-rt (riscv32imafc, no features)
run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imafc-unknown-none-elf
run: cd esp-riscv-rt/ && cargo build --target=riscv32imafc-unknown-none-elf
# Build for all RISC-V targets (all features):
- name: Build esp-riscv-rt (riscv32imc, all features)
run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imc-unknown-none-elf --features=ci
run: cd esp-riscv-rt/ && cargo build --target=riscv32imc-unknown-none-elf --features=ci
- name: Build esp-riscv-rt (riscv32imac, all features)
run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imac-unknown-none-elf --features=ci
run: cd esp-riscv-rt/ && cargo build --target=riscv32imac-unknown-none-elf --features=ci
- name: Build esp-riscv-rt (riscv32imafc, all features)
run: cd esp-riscv-rt/ && cargo build -Zbuild-std=core --target=riscv32imafc-unknown-none-elf --features=ci
run: cd esp-riscv-rt/ && cargo build --target=riscv32imafc-unknown-none-elf --features=ci
# Ensure documentation can be built
- name: rustdoc
run: cd esp-riscv-rt/ && cargo doc

3
esp-ieee802154/Cargo.toml
View File

@ -29,3 +29,6 @@ vcell = "0.1.3"
default = []
esp32c6 = ["esp-hal/esp32c6", "esp-wifi-sys/esp32c6"]
esp32h2 = ["esp-hal/esp32h2", "esp-wifi-sys/esp32h2"]
## Output logging from the phy blobs. Requires nightly
binary-logs = []

260
esp-ieee802154/src/compat/mod.rs
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@ -1,130 +1,146 @@
use core::{ffi::VaListImpl, fmt::Write};
use log::info;
use self::str_buf::StrBuf;
#[cfg(feature = "binary-logs")]
mod str_buf;
#[no_mangle]
pub unsafe extern "C" fn phy_printf(format: *const u8, args: ...) {
syslog(format, args);
}
#[cfg(feature = "binary-logs")]
mod binary_logs {
use core::{ffi::VaListImpl, fmt::Write};
#[no_mangle]
pub unsafe extern "C" fn rtc_printf(format: *const u8, args: ...) {
syslog(format, args);
}
use log::info;
#[no_mangle]
pub unsafe extern "C" fn coexist_printf(format: *const u8, args: ...) {
syslog(format, args);
}
use super::str_buf::StrBuf;
pub unsafe extern "C" fn syslog(format: *const u8, args: VaListImpl) {
let mut buf = [0u8; 512];
vsnprintf(&mut buf as *mut u8, 511, format, args);
let res_str = StrBuf::from(&buf as *const u8);
info!("{}", res_str.as_str_ref());
}
pub(crate) unsafe fn vsnprintf(
dst: *mut u8,
_n: u32,
format: *const u8,
mut args: VaListImpl,
) -> i32 {
let fmt_str_ptr = format;
let mut res_str = StrBuf::new();
let strbuf = StrBuf::from(fmt_str_ptr);
let s = strbuf.as_str_ref();
let mut format_char = ' ';
let mut is_long = false;
let mut found = false;
for c in s.chars() {
if !found {
if c == '%' {
found = true;
}
if !found {
res_str.append_char(c);
}
} else if c.is_numeric() || c == '-' || c == 'l' {
if c == 'l' {
is_long = true;
}
// ignore
} else {
// a format char
format_char = c;
}
if found && format_char != ' ' {
// have to format an arg
match format_char {
'd' => {
if is_long {
let v = args.arg::<i64>();
write!(res_str, "{}", v).ok();
} else {
let v = args.arg::<i32>();
write!(res_str, "{}", v).ok();
}
}
'u' => {
let v = args.arg::<u32>();
write!(res_str, "{}", v).ok();
}
'p' => {
let v = args.arg::<u32>();
write!(res_str, "0x{:x}", v).ok();
}
'X' => {
let v = args.arg::<u32>();
write!(res_str, "{:02x}", (v & 0xff000000) >> 24).ok();
}
'x' => {
let v = args.arg::<u32>();
write!(res_str, "{:02x}", v).ok();
}
's' => {
let v = args.arg::<u32>() as *const u8;
let vbuf = StrBuf::from(v);
write!(res_str, "{}", vbuf.as_str_ref()).ok();
}
'c' => {
let v = args.arg::<u8>();
if v != 0 {
write!(res_str, "{}", v as char).ok();
}
}
_ => {
write!(res_str, "<UNKNOWN{}>", format_char).ok();
}
}
format_char = ' ';
found = false;
is_long = false;
}
#[no_mangle]
pub unsafe extern "C" fn phy_printf(_format: *const u8, _args: ...) {
syslog(_format, _args);
}
let mut idx = 0;
res_str.as_str_ref().chars().for_each(|c| {
*(dst.offset(idx)) = c as u8;
idx += 1;
});
*(dst.offset(idx)) = 0;
idx as i32
#[no_mangle]
pub unsafe extern "C" fn rtc_printf(_format: *const u8, _args: ...) {
#[cfg(feature = "binary-logs")]
syslog(_format, _args);
}
#[no_mangle]
pub unsafe extern "C" fn coexist_printf(_format: *const u8, _args: ...) {
#[cfg(feature = "binary-logs")]
syslog(_format, _args);
}
pub unsafe extern "C" fn syslog(format: *const u8, args: VaListImpl) {
let mut buf = [0u8; 512];
vsnprintf(&mut buf as *mut u8, 511, format, args);
let res_str = StrBuf::from(&buf as *const u8);
info!("{}", res_str.as_str_ref());
}
pub(crate) unsafe fn vsnprintf(
dst: *mut u8,
_n: u32,
format: *const u8,
mut args: VaListImpl,
) -> i32 {
let fmt_str_ptr = format;
let mut res_str = StrBuf::new();
let strbuf = StrBuf::from(fmt_str_ptr);
let s = strbuf.as_str_ref();
let mut format_char = ' ';
let mut is_long = false;
let mut found = false;
for c in s.chars() {
if !found {
if c == '%' {
found = true;
}
if !found {
res_str.append_char(c);
}
} else if c.is_numeric() || c == '-' || c == 'l' {
if c == 'l' {
is_long = true;
}
// ignore
} else {
// a format char
format_char = c;
}
if found && format_char != ' ' {
// have to format an arg
match format_char {
'd' => {
if is_long {
let v = args.arg::<i64>();
write!(res_str, "{}", v).ok();
} else {
let v = args.arg::<i32>();
write!(res_str, "{}", v).ok();
}
}
'u' => {
let v = args.arg::<u32>();
write!(res_str, "{}", v).ok();
}
'p' => {
let v = args.arg::<u32>();
write!(res_str, "0x{:x}", v).ok();
}
'X' => {
let v = args.arg::<u32>();
write!(res_str, "{:02x}", (v & 0xff000000) >> 24).ok();
}
'x' => {
let v = args.arg::<u32>();
write!(res_str, "{:02x}", v).ok();
}
's' => {
let v = args.arg::<u32>() as *const u8;
let vbuf = StrBuf::from(v);
write!(res_str, "{}", vbuf.as_str_ref()).ok();
}
'c' => {
let v = args.arg::<u8>();
if v != 0 {
write!(res_str, "{}", v as char).ok();
}
}
_ => {
write!(res_str, "<UNKNOWN{}>", format_char).ok();
}
}
format_char = ' ';
found = false;
is_long = false;
}
}
let mut idx = 0;
res_str.as_str_ref().chars().for_each(|c| {
*(dst.offset(idx)) = c as u8;
idx += 1;
});
*(dst.offset(idx)) = 0;
idx as i32
}
}
#[cfg(not(feature = "binary-logs"))]
mod dummy {
#[no_mangle]
pub unsafe extern "C" fn phy_printf(_format: *const u8, _args: *const ()) {}
#[no_mangle]
pub unsafe extern "C" fn rtc_printf(_format: *const u8, _args: *const ()) {}
#[no_mangle]
pub unsafe extern "C" fn coexist_printf(_format: *const u8, _args: *const ()) {}
}

2
esp-ieee802154/src/lib.rs
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@ -6,7 +6,7 @@
//! [IEEE 802.15.4]: https://en.wikipedia.org/wiki/IEEE_802.15.4
#![no_std]
#![feature(c_variadic)]
#![cfg_attr(feature = "binary-logs", feature(c_variadic))]
use core::{cell::RefCell, marker::PhantomData};

1
examples/src/bin/embassy_i2c_bmp180_calibration_data.rs
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@ -16,7 +16,6 @@
#![no_std]
#![no_main]
#![feature(type_alias_impl_trait)]
use embassy_executor::Spawner;
use embassy_time::{Duration, Timer};

1
examples/src/bin/spi_slave_dma.rs
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@ -28,7 +28,6 @@
#![no_std]
#![no_main]
#![feature(asm_experimental_arch)]
use esp_backtrace as _;
use esp_hal::{

11
xtask/src/lib.rs
View File

@ -21,6 +21,7 @@ pub enum Package {
EspHal,
EspHalProcmacros,
EspHalSmartled,
EspIeee802154,
EspLpHal,
EspRiscvRt,
Examples,
@ -158,7 +159,6 @@ pub fn build_documentation(
// Build up an array of command-line arguments to pass to `cargo`:
let mut builder = CargoArgsBuilder::default()
.subcommand("doc")
.arg("-Zbuild-std=core") // Required for Xtensa, for some reason
.target(target)
.features(&features);
@ -169,6 +169,7 @@ pub fn build_documentation(
// If targeting an Xtensa device, we must use the '+esp' toolchain modifier:
if target.starts_with("xtensa") {
builder = builder.toolchain("esp");
builder = builder.arg("-Zbuild-std=core,alloc")
}
let args = builder.build();
@ -270,7 +271,6 @@ pub fn execute_app(
let mut builder = CargoArgsBuilder::default()
.subcommand(subcommand)
.arg("-Zbuild-std=alloc,core")
.arg("--release")
.target(target)
.features(&features)
@ -289,6 +289,7 @@ pub fn execute_app(
// If targeting an Xtensa device, we must use the '+esp' toolchain modifier:
if target.starts_with("xtensa") {
builder = builder.toolchain("esp");
builder = builder.arg("-Zbuild-std=core,alloc")
}
let args = builder.build();
@ -316,7 +317,6 @@ pub fn build_package(
let mut builder = CargoArgsBuilder::default()
.subcommand("build")
.arg("-Zbuild-std=core")
.arg("--release");
if let Some(toolchain) = toolchain {
@ -324,6 +324,11 @@ pub fn build_package(
}
if let Some(target) = target {
// If targeting an Xtensa device, we must use the '+esp' toolchain modifier:
if target.starts_with("xtensa") {
builder = builder.toolchain("esp");
builder = builder.arg("-Zbuild-std=core,alloc")
}
builder = builder.target(target);
}