From f1ec4a2ac9aa6dbffbaa241c4227804f86fa2a41 Mon Sep 17 00:00:00 2001 From: Kirill Mikhailov <62840029+playfulFence@users.noreply.github.com> Date: Wed, 14 Aug 2024 18:38:00 +0200 Subject: [PATCH] Removing raw addresses manipulations - part 3 (#1892) * WIP state * More fixes * Roll back `esp-storage` changes * Small fixes Will not work, needs another patch for PACs * update pacs dep * Lint * Get rid of unnecessary if-else fix * New pacs version --- esp-hal/Cargo.toml | 14 ++-- esp-hal/src/interrupt/riscv.rs | 101 +++++++++++------------- esp-hal/src/rtc_cntl/sleep/esp32c3.rs | 50 ++++-------- esp-hal/src/rtc_cntl/sleep/esp32s3.rs | 50 ++++-------- esp-hal/src/soc/esp32c6/radio_clocks.rs | 6 +- esp-hal/src/soc/esp32h2/radio_clocks.rs | 6 +- esp-wifi/src/wifi/os_adapter_esp32.rs | 25 +++--- 7 files changed, 99 insertions(+), 153 deletions(-) diff --git a/esp-hal/Cargo.toml b/esp-hal/Cargo.toml index 525f41cba..11a516cfa 100644 --- a/esp-hal/Cargo.toml +++ b/esp-hal/Cargo.toml @@ -53,13 +53,13 @@ xtensa-lx = { version = "0.9.0", optional = true } # IMPORTANT: # Each supported device MUST have its PAC included below along with a # corresponding feature. -esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } -esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "5270c86", features = ["critical-section", "rt"], optional = true } +esp32 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32c2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32c3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32c6 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32h2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32s2 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } +esp32s3 = { git = "https://github.com/esp-rs/esp-pacs", rev = "e3741e6", features = ["critical-section", "rt"], optional = true } [target.'cfg(target_arch = "riscv32")'.dependencies] esp-riscv-rt = { version = "0.9.0", path = "../esp-riscv-rt" } diff --git a/esp-hal/src/interrupt/riscv.rs b/esp-hal/src/interrupt/riscv.rs index 6b9f8da77..19e062ef5 100644 --- a/esp-hal/src/interrupt/riscv.rs +++ b/esp-hal/src/interrupt/riscv.rs @@ -572,12 +572,8 @@ mod classic { /// priority of interrupts 1 - 15. pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) { let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; - let cpu_interrupt_number = which as isize; - let intr_prio_base = intr.cpu_int_pri(0).as_ptr(); - - intr_prio_base - .offset(cpu_interrupt_number) - .write_volatile(priority as u32); + intr.cpu_int_pri(which as usize) + .write(|w| w.map().bits(priority as u8)); } /// Clear a CPU interrupt @@ -601,12 +597,9 @@ mod classic { #[inline] pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority { let intr = &*crate::peripherals::INTERRUPT_CORE0::PTR; - let intr_prio_base = intr.cpu_int_pri(0).as_ptr(); - - let prio = intr_prio_base - .offset(cpu_interrupt as isize) - .read_volatile(); - core::mem::transmute::(prio as u8) + core::mem::transmute::( + intr.cpu_int_pri(cpu_interrupt as usize).read().map().bits(), + ) } #[no_mangle] #[link_section = ".trap"] @@ -659,22 +652,19 @@ mod plic { 1, 2, 0, 0, 3, 4, 0, 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ]; - const DR_REG_PLIC_MX_BASE: u32 = 0x20001000; - const PLIC_MXINT_ENABLE_REG: u32 = DR_REG_PLIC_MX_BASE; - const PLIC_MXINT_TYPE_REG: u32 = DR_REG_PLIC_MX_BASE + 0x4; - const PLIC_MXINT_CLEAR_REG: u32 = DR_REG_PLIC_MX_BASE + 0x8; - const PLIC_MXINT0_PRI_REG: u32 = DR_REG_PLIC_MX_BASE + 0x10; - const PLIC_MXINT_THRESH_REG: u32 = DR_REG_PLIC_MX_BASE + 0x90; /// Enable a CPU interrupt /// /// # Safety /// /// Make sure there is an interrupt handler registered. pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) { - let cpu_interrupt_number = which as isize; - let mxint_enable = PLIC_MXINT_ENABLE_REG as *mut u32; unsafe { - mxint_enable.write_volatile(mxint_enable.read_volatile() | 1 << cpu_interrupt_number); + let plic = &*crate::peripherals::PLIC_MX::PTR; + plic.mxint_enable().modify(|r, w| { + let old = r.cpu_mxint_enable().bits(); + let new = old | 1 << (which as isize); + w.cpu_mxint_enable().bits(new) + }); } } @@ -684,17 +674,17 @@ mod plic { /// bits. pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) { unsafe { - let intr = PLIC_MXINT_TYPE_REG as *mut u32; - let cpu_interrupt_number = which as isize; - + let plic = &*crate::peripherals::PLIC_MX::PTR; let interrupt_type = match kind { InterruptKind::Level => 0, InterruptKind::Edge => 1, }; - intr.write_volatile( - intr.read_volatile() & !(1 << cpu_interrupt_number) - | (interrupt_type << cpu_interrupt_number), - ); + + plic.mxint_type().modify(|r, w| { + let old = r.cpu_mxint_type().bits(); + let new = old & !(1 << (which as isize)) | (interrupt_type << (which as isize)); + w.cpu_mxint_type().bits(new) + }); } } @@ -705,21 +695,23 @@ mod plic { /// Great care must be taken when using this function; avoid changing the /// priority of interrupts 1 - 15. pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) { - let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32; - - let cpu_interrupt_number = which as isize; - plic_mxint_pri_ptr - .offset(cpu_interrupt_number) - .write_volatile(priority as u32); + unsafe { + let plic = &*crate::peripherals::PLIC_MX::PTR; + plic.mxint_pri(which as usize) + .modify(|_, w| w.cpu_mxint_pri().bits(priority as u8)); + } } /// Clear a CPU interrupt #[inline] pub fn clear(_core: Cpu, which: CpuInterrupt) { unsafe { - let cpu_interrupt_number = which as isize; - let intr = PLIC_MXINT_CLEAR_REG as *mut u32; - intr.write_volatile(1 << cpu_interrupt_number); + let plic = &*crate::peripherals::PLIC_MX::PTR; + plic.mxint_clear().modify(|r, w| { + let old = r.cpu_mxint_clear().bits(); + let new = old | (1 << (which as isize)); + w.cpu_mxint_clear().bits(new) + }); } } @@ -735,40 +727,41 @@ mod plic { /// Get interrupt priority - called by assembly code #[inline] pub(super) unsafe extern "C" fn get_priority(cpu_interrupt: CpuInterrupt) -> Priority { - let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32; - - let cpu_interrupt_number = cpu_interrupt as isize; - let prio = plic_mxint_pri_ptr - .offset(cpu_interrupt_number) - .read_volatile(); - core::mem::transmute::(prio as u8) + let plic = &*crate::peripherals::PLIC_MX::PTR; + let prio = plic + .mxint_pri(cpu_interrupt as usize) + .read() + .cpu_mxint_pri() + .bits(); + core::mem::transmute::(prio) } #[no_mangle] #[link_section = ".trap"] pub(super) unsafe extern "C" fn _handle_priority() -> u32 { use super::mcause; - let plic_mxint_pri_ptr = PLIC_MXINT0_PRI_REG as *mut u32; - let interrupt_id: isize = unwrap!(mcause::read().code().try_into()); // MSB is whether its exception or interrupt. - let interrupt_priority = plic_mxint_pri_ptr.offset(interrupt_id).read_volatile(); + let plic = &*crate::peripherals::PLIC_MX::PTR; - let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32; - let prev_interrupt_priority = thresh_reg.read_volatile() & 0x000000FF; - // this is a u8 according to esp-idf, so mask everything else. + let interrupt_id: usize = mcause::read().code(); // MSB is whether its exception or interrupt. + let interrupt_priority = plic.mxint_pri(interrupt_id).read().cpu_mxint_pri().bits(); + + let prev_interrupt_priority = plic.mxint_thresh().read().cpu_mxint_thresh().bits(); if interrupt_priority < 15 { // leave interrupts disabled if interrupt is of max priority. - thresh_reg.write_volatile(interrupt_priority + 1); + plic.mxint_thresh() + .write(|w| w.cpu_mxint_thresh().bits(interrupt_priority + 1)); unsafe { riscv::interrupt::enable(); } } - prev_interrupt_priority + prev_interrupt_priority as u32 } #[no_mangle] #[link_section = ".trap"] pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) { riscv::interrupt::disable(); - let thresh_reg = PLIC_MXINT_THRESH_REG as *mut u32; - thresh_reg.write_volatile(stored_prio); + let plic = &*crate::peripherals::PLIC_MX::PTR; + plic.mxint_thresh() + .write(|w| w.cpu_mxint_thresh().bits(stored_prio as u8)); } } diff --git a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs index f8fdcf3fa..e5a0c89ef 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32c3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32c3.rs @@ -387,42 +387,16 @@ impl Default for RtcSleepConfig { } } -const DR_REG_NRX_BASE: u32 = 0x6001CC00; -const DR_REG_FE_BASE: u32 = 0x60006000; -const DR_REG_FE2_BASE: u32 = 0x60005000; - -const NRXPD_CTRL: u32 = DR_REG_NRX_BASE + 0x00d4; -const FE_GEN_CTRL: u32 = DR_REG_FE_BASE + 0x0090; -const FE2_TX_INTERP_CTRL: u32 = DR_REG_FE2_BASE + 0x00f0; - const SYSCON_SRAM_POWER_UP: u8 = 0x0000000F; const SYSCON_ROM_POWER_UP: u8 = 0x00000003; -const NRX_RX_ROT_FORCE_PU: u32 = 1 << 5; -const NRX_VIT_FORCE_PU: u32 = 1 << 3; -const NRX_DEMAP_FORCE_PU: u32 = 1 << 1; - -const FE_IQ_EST_FORCE_PU: u32 = 1 << 5; -const FE2_TX_INF_FORCE_PU: u32 = 1 << 10; - -fn modify_register(reg: u32, mask: u32, value: u32) { - let reg = reg as *mut u32; - - unsafe { reg.write_volatile((reg.read_volatile() & !mask) | value) }; -} - -fn register_modify_bits(reg: u32, bits: u32, set: bool) { - if set { - modify_register(reg, bits, bits); - } else { - modify_register(reg, bits, 0); - } -} - fn rtc_sleep_pu(val: bool) { let rtc_cntl = unsafe { &*esp32c3::RTC_CNTL::ptr() }; let syscon = unsafe { &*esp32c3::APB_CTRL::ptr() }; let bb = unsafe { &*esp32c3::BB::ptr() }; + let nrx = unsafe { &*esp32c3::NRX::ptr() }; + let fe = unsafe { &*esp32c3::FE::ptr() }; + let fe2 = unsafe { &*esp32c3::FE2::ptr() }; rtc_cntl .dig_pwc() @@ -440,15 +414,19 @@ fn rtc_sleep_pu(val: bool) { bb.bbpd_ctrl() .modify(|_r, w| w.fft_force_pu().bit(val).dc_est_force_pu().bit(val)); - register_modify_bits( - NRXPD_CTRL, - NRX_RX_ROT_FORCE_PU | NRX_VIT_FORCE_PU | NRX_DEMAP_FORCE_PU, - val, - ); + nrx.nrxpd_ctrl().modify(|_, w| { + w.rx_rot_force_pu() + .bit(val) + .vit_force_pu() + .bit(val) + .demap_force_pu() + .bit(val) + }); - register_modify_bits(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, val); + fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().bit(val)); - register_modify_bits(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, val); + fe2.tx_interp_ctrl() + .modify(|_, w| w.tx_inf_force_pu().bit(val)); syscon.mem_power_up().modify(|_r, w| unsafe { w.sram_power_up() diff --git a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs index 34011d6cf..23a958582 100644 --- a/esp-hal/src/rtc_cntl/sleep/esp32s3.rs +++ b/esp-hal/src/rtc_cntl/sleep/esp32s3.rs @@ -328,42 +328,16 @@ impl Default for RtcSleepConfig { } } -const DR_REG_NRX_BASE: u32 = 0x6001CC00; -const DR_REG_FE_BASE: u32 = 0x60006000; -const DR_REG_FE2_BASE: u32 = 0x60005000; - -const NRXPD_CTRL: u32 = DR_REG_NRX_BASE + 0x00d4; -const FE_GEN_CTRL: u32 = DR_REG_FE_BASE + 0x0090; -const FE2_TX_INTERP_CTRL: u32 = DR_REG_FE2_BASE + 0x00f0; - const SYSCON_SRAM_POWER_UP: u16 = 0x7FF; const SYSCON_ROM_POWER_UP: u8 = 0x7; -const NRX_RX_ROT_FORCE_PU: u32 = 1 << 5; -const NRX_VIT_FORCE_PU: u32 = 1 << 3; -const NRX_DEMAP_FORCE_PU: u32 = 1 << 1; - -const FE_IQ_EST_FORCE_PU: u32 = 1 << 5; -const FE2_TX_INF_FORCE_PU: u32 = 1 << 10; - -fn modify_register(reg: u32, mask: u32, value: u32) { - let reg = reg as *mut u32; - - unsafe { reg.write_volatile((reg.read_volatile() & !mask) | value) }; -} - -fn register_modify_bits(reg: u32, bits: u32, set: bool) { - if set { - modify_register(reg, bits, bits); - } else { - modify_register(reg, bits, 0); - } -} - fn rtc_sleep_pu(val: bool) { let rtc_cntl = unsafe { &*esp32s3::RTC_CNTL::ptr() }; let syscon = unsafe { &*esp32s3::APB_CTRL::ptr() }; let bb = unsafe { &*esp32s3::BB::ptr() }; + let nrx = unsafe { &*esp32s3::NRX::ptr() }; + let fe = unsafe { &*esp32s3::FE::ptr() }; + let fe2 = unsafe { &*esp32s3::FE2::ptr() }; rtc_cntl .dig_pwc() @@ -385,15 +359,19 @@ fn rtc_sleep_pu(val: bool) { bb.bbpd_ctrl() .modify(|_r, w| w.fft_force_pu().bit(val).dc_est_force_pu().bit(val)); - register_modify_bits( - NRXPD_CTRL, - NRX_RX_ROT_FORCE_PU | NRX_VIT_FORCE_PU | NRX_DEMAP_FORCE_PU, - val, - ); + nrx.nrxpd_ctrl().modify(|_, w| { + w.rx_rot_force_pu() + .bit(val) + .vit_force_pu() + .bit(val) + .demap_force_pu() + .bit(val) + }); - register_modify_bits(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, val); + fe.gen_ctrl().modify(|_, w| w.iq_est_force_pu().bit(val)); - register_modify_bits(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, val); + fe2.tx_interp_ctrl() + .modify(|_, w| w.tx_inf_force_pu().bit(val)); syscon.mem_power_up().modify(|_r, w| unsafe { w.sram_power_up() diff --git a/esp-hal/src/soc/esp32c6/radio_clocks.rs b/esp-hal/src/soc/esp32c6/radio_clocks.rs index 2ce532a78..f9319969b 100644 --- a/esp-hal/src/soc/esp32c6/radio_clocks.rs +++ b/esp-hal/src/soc/esp32c6/radio_clocks.rs @@ -342,11 +342,9 @@ fn init_clocks() { pmu.hp_active_icg_modem() .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); pmu.imm_modem_icg() - .as_ptr() - .write_volatile(pmu.imm_modem_icg().as_ptr().read_volatile() | 1 << 31); + .write(|w| w.update_dig_icg_modem_en().set_bit()); pmu.imm_sleep_sysclk() - .as_ptr() - .write_volatile(pmu.imm_sleep_sysclk().as_ptr().read_volatile() | 1 << 28); + .write(|w| w.update_dig_icg_switch().set_bit()); let modem_syscon = &*esp32c6::MODEM_SYSCON::PTR; modem_syscon.clk_conf_power_st().modify(|_, w| { diff --git a/esp-hal/src/soc/esp32h2/radio_clocks.rs b/esp-hal/src/soc/esp32h2/radio_clocks.rs index d9067deab..101e7ee20 100644 --- a/esp-hal/src/soc/esp32h2/radio_clocks.rs +++ b/esp-hal/src/soc/esp32h2/radio_clocks.rs @@ -131,11 +131,9 @@ fn init_clocks() { pmu.hp_active_icg_modem() .modify(|_, w| w.hp_active_dig_icg_modem_code().bits(2)); pmu.imm_modem_icg() - .as_ptr() - .write_volatile(pmu.imm_modem_icg().as_ptr().read_volatile() | 1 << 31); + .write(|w| w.update_dig_icg_modem_en().set_bit()); pmu.imm_sleep_sysclk() - .as_ptr() - .write_volatile(pmu.imm_sleep_sysclk().as_ptr().read_volatile() | 1 << 28); + .write(|w| w.update_dig_icg_switch().set_bit()); (*esp32h2::MODEM_LPCON::PTR).clk_conf().modify(|_, w| { w.clk_i2c_mst_en() diff --git a/esp-wifi/src/wifi/os_adapter_esp32.rs b/esp-wifi/src/wifi/os_adapter_esp32.rs index 6ef40ee33..f91e0b515 100644 --- a/esp-wifi/src/wifi/os_adapter_esp32.rs +++ b/esp-wifi/src/wifi/os_adapter_esp32.rs @@ -4,12 +4,7 @@ use crate::hal::{interrupt, peripherals}; -const DR_REG_DPORT_BASE: u32 = 0x3ff00000; -const DPORT_WIFI_CLK_EN_REG: u32 = DR_REG_DPORT_BASE + 0x0CC; -const DPORT_WIFI_CLK_WIFI_EN: u32 = 0x00000406; -const DPORT_WIFI_CLK_WIFI_EN_V: u32 = 0x406; -const DPORT_WIFI_CLK_WIFI_EN_S: u32 = 0; -const DPORT_WIFI_CLK_WIFI_EN_M: u32 = (DPORT_WIFI_CLK_WIFI_EN_V) << (DPORT_WIFI_CLK_WIFI_EN_S); +const DPORT_WIFI_CLK_WIFI_EN_M: u32 = 0x406; pub(crate) fn chip_ints_on(mask: u32) { unsafe { crate::hal::xtensa_lx::interrupt::enable_mask(mask) }; @@ -56,15 +51,21 @@ pub(crate) unsafe extern "C" fn set_intr( } pub(crate) unsafe extern "C" fn wifi_clock_enable() { - let ptr = DPORT_WIFI_CLK_EN_REG as *mut u32; - let old = ptr.read_volatile(); - ptr.write_volatile(old | DPORT_WIFI_CLK_WIFI_EN_M); + let dport = &*crate::hal::peripherals::SYSTEM::ptr(); + dport.wifi_clk_en().modify(|r, w| { + let old = r.bits(); + let new_bits = old | DPORT_WIFI_CLK_WIFI_EN_M; + w.bits(new_bits) + }); } pub(crate) unsafe extern "C" fn wifi_clock_disable() { - let ptr = DPORT_WIFI_CLK_EN_REG as *mut u32; - let old = ptr.read_volatile(); - ptr.write_volatile(old & !DPORT_WIFI_CLK_WIFI_EN_M); + let dport = &*crate::hal::peripherals::SYSTEM::ptr(); + dport.wifi_clk_en().modify(|r, w| { + let old = r.bits(); + let new_bits = old & !DPORT_WIFI_CLK_WIFI_EN_M; + w.bits(new_bits) + }); } /// **************************************************************************