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Remove the mcu-boot feature from esp32c3-hal (#938)

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* Remove the `mcu-boot` feature from `esp32c3-hal`

* Update `CHANGELOG.md`
This commit is contained in:
Jesse Braham 2023-11-14 11:49:40 -08:00 committed by GitHub
parent 52da17075e
commit f729f89889
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GPG Key ID: 4AEE18F83AFDEB23
9 changed files with 2 additions and 511 deletions
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4
.github/workflows/ci.yml vendored
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@ -177,12 +177,8 @@ jobs:
# Perform a full build initially to verify that the examples not only
# build, but also link successfully.
# We also use this as an opportunity to verify that the examples link
# for each supported image format.
- name: build esp32c3-hal (no features)
run: cd esp32c3-hal/ && cargo +nightly build --examples
- name: build esp32c3-hal (mcu-boot)
run: cd esp32c3-hal/ && cargo +nightly build --examples --features=mcu-boot
# Subsequent steps can just check the examples instead, as we're already
# confident that they link.
- name: check esp32c3-hal (common features)

2
CHANGELOG.md
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@ -31,6 +31,8 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
### Removed
- Removed the `mcu-boot` feature from `esp32c3-hal` (#938)
### Breaking
- Direct boot support has been removed (#903).
- `Spi::new`/`Spi::new_half_duplex` takes no gpio pin now, instead you need to call `with_pins` to setup those (#901).

1
esp32c3-hal/Cargo.toml
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@ -63,7 +63,6 @@ direct-vectoring = ["esp-hal-common/direct-vectoring"]
eh1 = ["esp-hal-common/eh1"]
interrupt-preemption = ["esp-hal-common/interrupt-preemption"]
log = ["esp-hal-common/log", "esp-println/log"]
mcu-boot = []
rt = []
ufmt = ["esp-hal-common/ufmt"]
vectored = ["esp-hal-common/vectored"]

24
esp32c3-hal/build.rs
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@ -1,6 +1,5 @@
use std::{env, error::Error, fs, path::PathBuf};
#[cfg(not(feature = "mcu-boot"))]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
@ -21,26 +20,3 @@ fn main() -> Result<(), Box<dyn Error>> {
Ok(())
}
#[cfg(feature = "mcu-boot")]
fn main() -> Result<(), Box<dyn Error>> {
// Put the linker script somewhere the linker can find it
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
println!("cargo:rustc-link-search={}", out.display());
fs::copy("ld/mb-esp32c3-memory.x", out.join("memory.x"))?;
fs::copy("ld/mb-esp32c3-link.x", out.join("esp32c3-link.x"))?;
fs::copy("ld/mb-riscv-link.x", out.join("riscv-link.x"))?;
fs::copy("ld/mb-linkall.x", out.join("linkall.x"))?;
fs::copy("ld/rom-functions.x", out.join("rom-functions.x"))?;
// Only re-run the build script when memory.x is changed,
// instead of when any part of the source code changes.
println!("cargo:rerun-if-changed=ld/memory.x");
#[cfg(feature = "defmt")]
println!("cargo:rustc-link-arg=-Tdefmt.x");
Ok(())
}

45
esp32c3-hal/ld/mb-esp32c3-link.x
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@ -1,45 +0,0 @@
INCLUDE memory.x
SECTIONS
{
.metadata :
{
/* Magic for load header */
LONG(0xace637d3)
/* Application entry point address */
KEEP(*(.entry_addr))
/* IRAM metadata:
* - Destination address (VMA) for IRAM region
* - Flash offset (LMA) for start of IRAM region
* - Size of IRAM region
*/
LONG(ADDR(.rwtext))
LONG(LOADADDR(.rwtext))
LONG(SIZEOF(.rwtext))
/* DRAM metadata:
* - Destination address (VMA) for DRAM region
* - Flash offset (LMA) for start of DRAM region
* - Size of DRAM region
*/
LONG(ADDR(.data))
LONG(LOADADDR(.data))
LONG(SIZEOF(.data))
} > metadata
}
INCLUDE riscv-link.x
_image_drom_vma = ADDR(.rodata);
_image_drom_lma = LOADADDR(.rodata);
_image_drom_size = LOADADDR(.rodata) + SIZEOF(.rodata) - _image_drom_lma;
_image_irom_vma = ADDR(.text);
_image_irom_lma = LOADADDR(.text);
_image_irom_size = LOADADDR(.text) + SIZEOF(.text) - _image_irom_lma;

65
esp32c3-hal/ld/mb-esp32c3-memory.x
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@ -1,65 +0,0 @@
MEMORY
{
/*
https://github.com/espressif/esptool/blob/ed64d20b051d05f3f522bacc6a786098b562d4b8/esptool/targets/esp32c3.py#L78-L90
MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"],
[0x3C000000, 0x3C800000, "DROM"],
[0x3FC80000, 0x3FCE0000, "DRAM"],
[0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
[0x3FF00000, 0x3FF20000, "DROM_MASK"],
[0x40000000, 0x40060000, "IROM_MASK"],
[0x42000000, 0x42800000, "IROM"],
[0x4037C000, 0x403E0000, "IRAM"],
[0x50000000, 0x50002000, "RTC_IRAM"],
[0x50000000, 0x50002000, "RTC_DRAM"],
[0x600FE000, 0x60100000, "MEM_INTERNAL2"]]
*/
/* The origin values for "metadata" and "ROM" memory regions are the actual
* load addresses.
*
* NOTE: The memory region starting from 0x0 with 0x20 length is reserved
* for the MCUboot header, which will be prepended to the binary file by
* the "imgtool" during the signing of firmware image.
*/
metadata : ORIGIN = 0x20, LENGTH = 0x20
ROM : ORIGIN = 0x40, LENGTH = 0x400000 - 0x40
/* 400K of on soc RAM, 16K reserved for cache */
ICACHE : ORIGIN = 0x4037C000, LENGTH = 0x4000
/* Instruction RAM */
IRAM : ORIGIN = 0x4037C000 + 0x4000, LENGTH = 400K - 0x4000
/* Data RAM */
DRAM : ORIGIN = 0x3FC80000, LENGTH = 0x50000
/* External flash */
/* Instruction ROM */
IROM : ORIGIN = 0x42000000, LENGTH = 0x400000
/* Data ROM */
/* The DROM segment origin is offset by 0x40 for mirroring the actual ROM
* image layout:
* 0x0 - 0x1F : MCUboot header
* 0x20 - 0x3F : Application image metadata section
* 0x40 onwards: ROM code and data
* This is required to meet the following constraint from the external
* flash MMU:
* VMA % 64KB == LMA % 64KB
* i.e. the lower 16 bits of both the virtual address (address seen by the
* CPU) and the load address (physical address of the external flash) must
* be equal.
*/
DROM : ORIGIN = 0x3C000000 + 0x40, LENGTH = 0x400000 - 0x40
/* RTC fast memory (executable). Persists over deep sleep. */
RTC_FAST : ORIGIN = 0x50000000, LENGTH = 0x2000 /*- ESP_BOOTLOADER_RESERVE_RTC*/
}
REGION_ALIAS("REGION_TEXT", IROM);
REGION_ALIAS("REGION_RODATA", DROM);
REGION_ALIAS("REGION_DATA", DRAM);
REGION_ALIAS("REGION_BSS", DRAM);
REGION_ALIAS("REGION_STACK", DRAM);
REGION_ALIAS("REGION_RWTEXT", IRAM);
REGION_ALIAS("REGION_RTC_FAST", RTC_FAST);

3
esp32c3-hal/ld/mb-linkall.x
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@ -1,3 +0,0 @@
INCLUDE "esp32c3-link.x"
INCLUDE "hal-defaults.x"
INCLUDE "rom-functions.x"

239
esp32c3-hal/ld/mb-riscv-link.x
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@ -1,239 +0,0 @@
ENTRY(_start)
PROVIDE(_stack_start = ORIGIN(REGION_STACK) + LENGTH(REGION_STACK));
PROVIDE(_max_hart_id = 0);
PROVIDE(UserSoft = DefaultHandler);
PROVIDE(SupervisorSoft = DefaultHandler);
PROVIDE(MachineSoft = DefaultHandler);
PROVIDE(UserTimer = DefaultHandler);
PROVIDE(SupervisorTimer = DefaultHandler);
PROVIDE(MachineTimer = DefaultHandler);
PROVIDE(UserExternal = DefaultHandler);
PROVIDE(SupervisorExternal = DefaultHandler);
PROVIDE(MachineExternal = DefaultHandler);
PROVIDE(DefaultHandler = DefaultInterruptHandler);
PROVIDE(ExceptionHandler = DefaultExceptionHandler);
PROVIDE(__post_init = default_post_init);
/* A PAC/HAL defined routine that should initialize custom interrupt controller if needed. */
PROVIDE(_setup_interrupts = default_setup_interrupts);
/* # Multi-processing hook function
fn _mp_hook() -> bool;
This function is called from all the harts and must return true only for one hart,
which will perform memory initialization. For other harts it must return false
and implement wake-up in platform-dependent way (e.g. after waiting for a user interrupt).
*/
PROVIDE(_mp_hook = default_mp_hook);
/* # Start trap function override
By default uses the riscv crates default trap handler
but by providing the `_start_trap` symbol external crates can override.
*/
PROVIDE(_start_trap = default_start_trap);
SECTIONS
{
.rodata :
{
_srodata = .;
*(.srodata .srodata.*);
*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .rodata);
*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .rodata.*);
*(EXCLUDE_FILE (*libesp_riscv_rt-*.rlib:esp-riscv-rt.*) .rodata);
*(EXCLUDE_FILE (*libesp_riscv_rt-*.rlib:esp-riscv-rt.*) .rodata.*);
/* 4-byte align the end (VMA) of this section.
This is required by LLD to ensure the LMA of the following .data
section will have the correct alignment. */
. = ALIGN(4);
_erodata = .;
} > REGION_RODATA AT>ROM
.rwtext :
{
_srwtext = .;
/* Put reset handler first in .rwtext section so it ends up as the entry */
/* point of the program. */
KEEP(*(.init));
KEEP(*(.init.rust));
KEEP(*(.text.abort));
KEEP(*(.trap));
*(.trap.*);
. = ALIGN(4);
*libriscv-*.rlib:riscv.*(.literal .text .literal.* .text.*);
*libesp_riscv_rt-*.rlib:esp-riscv-rt.*(.literal .text .literal.* .text.*);
*(.rwtext);
. = ALIGN(4);
_erwtext = .;
} > REGION_RWTEXT AT>ROM
.rwtext.dummy (NOLOAD):
{
/* This section is required to skip .rwtext area because REGION_RWTEXT
* and REGION_BSS reflect the same address space on different buses.
*/
. = ORIGIN(REGION_BSS) + _erwtext - _srwtext;
} > REGION_BSS
.bss (NOLOAD) :
{
_bss_start = .;
*(.sbss .sbss.* .bss .bss.*);
. = ALIGN(4);
_bss_end = .;
} > REGION_BSS
.uninit (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
__suninit = .;
*(.uninit .uninit.*);
. = ALIGN(4);
__euninit = .;
} > REGION_BSS
.data :
{
_data_start = .;
/* Must be called __global_pointer$ for linker relaxations to work. */
PROVIDE(__global_pointer$ = . + 0x800);
*(.sdata .sdata.* .sdata2 .sdata2.*);
*(.data .data.*);
*libriscv-*.rlib:riscv.*(.rodata .rodata.*);
*libesp_riscv_rt-*.rlib:esp-riscv-rt.*(.rodata .rodata.*);
. = ALIGN(4);
_data_end = .;
} > REGION_DATA AT>ROM
/* fictitious region that represents the memory available for the stack */
.stack (NOLOAD) :
{
_estack = .;
. = ABSOLUTE(_stack_start);
_sstack = .;
} > REGION_STACK
.rtc_fast.text :
{
_srtc_fast_text = .;
*(.rtc_fast.literal .rtc_fast.text .rtc_fast.literal.* .rtc_fast.text.*)
. = ALIGN(4);
_ertc_fast_text = .;
} > REGION_RTC_FAST AT>ROM
.rtc_fast.data :
{
_rtc_fast_data_start = ABSOLUTE(.);
*(.rtc_fast.data .rtc_fast.data.*)
. = ALIGN(4);
_rtc_fast_data_end = ABSOLUTE(.);
} > REGION_RTC_FAST AT>ROM
.rtc_fast.bss (NOLOAD) : ALIGN(4)
{
_rtc_fast_bss_start = ABSOLUTE(.);
*(.rtc_fast.bss .rtc_fast.bss.*)
. = ALIGN(4);
_rtc_fast_bss_end = ABSOLUTE(.);
} > REGION_RTC_FAST
.rtc_fast.noinit (NOLOAD) : ALIGN(4)
{
*(.rtc_fast.noinit .rtc_fast.noinit.*)
} > REGION_RTC_FAST
/* The alignment of the "text" output section is forced to
* 0x00010000 (64KB) to ensure that it will be allocated at the beginning
* of the next available Flash block.
* This is required to meet the following constraint from the external
* flash MMU:
* VMA % 64KB == LMA % 64KB
* i.e. the lower 16 bits of both the virtual address (address seen by the
* CPU) and the load address (physical address of the external flash) must
* be equal.
*/
.text.dummy (NOLOAD) : ALIGN(0x10000)
{
/* This section is required to skip .rodata area because REGION_TEXT
* and REGION_RODATA reflect the same address space on different buses.
*/
. += SIZEOF(.rodata);
} > REGION_TEXT
.text : ALIGN(0x10000)
{
_stext = .;
*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .text)
*(EXCLUDE_FILE (*libriscv-*.rlib:riscv.*) .text.*)
*(EXCLUDE_FILE (*libesp_riscv_rt-*.rlib:esp-riscv-rt.*) .text)
*(EXCLUDE_FILE (*libesp_riscv_rt-*.rlib:esp-riscv-rt.*) .text.*)
_etext = .;
} > REGION_TEXT AT>ROM
/* fake output .got section */
/* Dynamic relocations are unsupported. This section is only used to detect
relocatable code in the input files and raise an error if relocatable code
is found */
.got (INFO) :
{
KEEP(*(.got .got.*));
}
.eh_frame (INFO) : { KEEP(*(.eh_frame)) }
.eh_frame_hdr (INFO) : { *(.eh_frame_hdr) }
}
PROVIDE(_sidata = _erodata + 8);
PROVIDE(_irwtext = ORIGIN(DROM) + _text_size + _rodata_size + _data_size);
PROVIDE(_irtc_fast_text = ORIGIN(DROM) + _text_size + _rodata_size + _data_size + _rwtext_size);
PROVIDE(_irtc_fast_data = ORIGIN(DROM) + _text_size + _rodata_size + _data_size + _rwtext_size + _fast_text_size);
/* Do not exceed this mark in the error messages above | */
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_RODATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_RODATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_DATA) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_DATA must be 4-byte aligned");
ASSERT(ORIGIN(REGION_TEXT) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_TEXT must be 4-byte aligned");
ASSERT(ORIGIN(REGION_STACK) % 4 == 0, "
ERROR(riscv-rt): the start of the REGION_STACK must be 4-byte aligned");
ASSERT(_stext % 4 == 0, "
ERROR(riscv-rt): `_stext` must be 4-byte aligned");
ASSERT(_data_start % 4 == 0 && _data_end % 4 == 0, "
BUG(riscv-rt): .data is not 4-byte aligned");
ASSERT(_sidata % 4 == 0, "
BUG(riscv-rt): the LMA of .data is not 4-byte aligned");
ASSERT(_bss_start % 4 == 0 && _bss_end % 4 == 0, "
BUG(riscv-rt): .bss is not 4-byte aligned");
ASSERT(_stext + SIZEOF(.text) < ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT), "
ERROR(riscv-rt): The .text section must be placed inside the REGION_TEXT region.
Set _stext to an address smaller than 'ORIGIN(REGION_TEXT) + LENGTH(REGION_TEXT)'");
ASSERT(SIZEOF(.got) == 0, "
.got section detected in the input files. Dynamic relocations are not
supported. If you are linking to C code compiled using the `gcc` crate
then modify your build script to compile the C code _without_ the
-fPIC flag. See the documentation of the `gcc::Config.fpic` method for
details.");
/* Do not exceed this mark in the error messages above | */

130
esp32c3-hal/src/lib.rs
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@ -23,7 +23,6 @@
//! peripheral
//! - `interrupt-preemption` - Enable priority-based interrupt preemption
//! - `log` - enable log output using the `log` crate
//! - `mcu-boot` - Use the MCUboot image format
//! - `rt` - Runtime support
//! - `ufmt` - Implement the [`ufmt_write::uWrite`] trait for the UART and USB
//! Serial JTAG drivers
@ -71,137 +70,8 @@
pub use esp_hal_common::*;
extern "C" {
cfg_if::cfg_if! {
if #[cfg(feature = "mcu-boot")] {
// Required for retrieving the entry point address
fn _start();
// Functions from internal ROM
fn cache_suspend_icache() -> u32;
fn cache_resume_icache(val: u32);
fn cache_invalidate_icache_all();
fn cache_dbus_mmu_set(
ext_ram: u32,
vaddr: u32,
paddr: u32,
psize: u32,
num: u32,
fixed: u32,
) -> i32;
fn cache_ibus_mmu_set(
ext_ram: u32,
vaddr: u32,
paddr: u32,
psize: u32,
num: u32,
fixed: u32,
) -> i32;
/* IROM metadata:
* - Destination address (VMA) for IROM region
* - Flash offset (LMA) for start of IROM region
* - Size of IROM region
*/
static mut _image_irom_vma: u32;
static mut _image_irom_lma: u32;
static mut _image_irom_size: u32;
/* DROM metadata:
* - Destination address (VMA) for DROM region
* - Flash offset (LMA) for start of DROM region
* - Size of DROM region
*/
static mut _image_drom_vma: u32;
static mut _image_drom_lma: u32;
static mut _image_drom_size: u32;
}
}
}
#[cfg(feature = "mcu-boot")]
#[link_section = ".entry_addr"]
#[no_mangle]
#[used]
// Entry point address for the MCUboot image header
static ENTRY_POINT: unsafe extern "C" fn() = _start;
#[cfg(feature = "mcu-boot")]
#[link_section = ".rwtext"]
unsafe fn configure_mmu() {
const PARTITION_OFFSET: u32 = 0x10000;
let app_irom_lma = PARTITION_OFFSET + ((&_image_irom_lma as *const u32) as u32);
let app_irom_size = (&_image_irom_size as *const u32) as u32;
let app_irom_vma = (&_image_irom_vma as *const u32) as u32;
let app_drom_lma = PARTITION_OFFSET + ((&_image_drom_lma as *const u32) as u32);
let app_drom_size = (&_image_drom_size as *const u32) as u32;
let app_drom_vma = (&_image_drom_vma as *const u32) as u32;
let autoload = cache_suspend_icache();
cache_invalidate_icache_all();
// Clear the MMU entries that are already set up, so the new app only has
// the mappings it creates.
const FLASH_MMU_TABLE: *mut u32 = 0x600c_5000 as *mut u32;
const ICACHE_MMU_SIZE: usize = 0x200;
const FLASH_MMU_TABLE_SIZE: usize = ICACHE_MMU_SIZE / core::mem::size_of::<u32>();
const MMU_TABLE_INVALID_VAL: u32 = 0x100;
for i in 0..FLASH_MMU_TABLE_SIZE {
FLASH_MMU_TABLE.add(i).write_volatile(MMU_TABLE_INVALID_VAL);
}
const MMU_BLOCK_SIZE: u32 = 0x0001_0000;
const MMU_FLASH_MASK: u32 = !(MMU_BLOCK_SIZE - 1);
let calc_mmu_pages = |size, vaddr| {
(size + (vaddr - (vaddr & MMU_FLASH_MASK)) + MMU_BLOCK_SIZE - 1) / MMU_BLOCK_SIZE
};
let drom_lma_aligned = app_drom_lma & MMU_FLASH_MASK;
let drom_vma_aligned = app_drom_vma & MMU_FLASH_MASK;
let drom_page_count = calc_mmu_pages(app_drom_size, app_drom_vma);
cache_dbus_mmu_set(
0,
drom_vma_aligned,
drom_lma_aligned,
64,
drom_page_count,
0,
);
let irom_lma_aligned = app_irom_lma & MMU_FLASH_MASK;
let irom_vma_aligned = app_irom_vma & MMU_FLASH_MASK;
let irom_page_count = calc_mmu_pages(app_irom_size, app_irom_vma);
cache_ibus_mmu_set(
0,
irom_vma_aligned,
irom_lma_aligned,
64,
irom_page_count,
0,
);
let extmem = unsafe { &*peripherals::EXTMEM::ptr() };
extmem.icache_ctrl1.modify(|_, w| {
w.icache_shut_ibus()
.clear_bit()
.icache_shut_dbus()
.clear_bit()
});
cache_resume_icache(autoload);
}
#[export_name = "__post_init"]
#[cfg_attr(feature = "mcu-boot", link_section = ".rwtext")]
unsafe fn post_init() {
#[cfg(feature = "mcu-boot")]
unsafe {
configure_mmu();
}
use esp_hal_common::{
peripherals::{RTC_CNTL, TIMG0, TIMG1},
timer::Wdt,