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Fix C6 clock related issues (#4579)

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* Use XTAL as default TIMG clock source

* Fix SPI clock source frequency
This commit is contained in:
Dániel Buga 2025-12-01 10:50:49 +01:00 committed by GitHub
parent 203ce79c5f
commit faca0aca7d
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GPG Key ID: B5690EEEBB952194
8 changed files with 39 additions and 20 deletions
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5
esp-hal/src/spi/master.rs
View File

@ -507,6 +507,11 @@ impl Config {
if #[cfg(esp32h2)] {
// ESP32-H2 is using PLL_48M_CLK source instead of APB_CLK
clocks.pll_48m_clock
} else if #[cfg(esp32c6)] {
// We select the 80MHz PLL as the clock source in the driver
// FIXME we state that the default clock source is APB, which just isn't true
let _clocks = clocks;
Rate::from_mhz(80)
} else {
clocks.apb_clock
}

42
esp-hal/src/timer/timg.rs
View File

@ -82,7 +82,10 @@ use crate::{
time::{Duration, Instant, Rate},
};
#[cfg(timergroup_default_clock_source_is_set)]
#[cfg(all(
timergroup_default_clock_source_is_set,
not(soc_has_clock_node_timg0_function_clock)
))]
const DEFAULT_CLK_SRC: u8 = property!("timergroup.default_clock_source");
#[cfg(timergroup_default_wdt_clock_source_is_set)]
const DEFAULT_WDT_CLK_SRC: u8 = property!("timergroup.default_wdt_clock_source");
@ -144,17 +147,16 @@ impl TimerGroupInstance for TIMG0<'_> {
}
fn configure_src_clk() {
#[cfg(soc_has_clock_node_timg0_function_clock)]
crate::soc::clocks::ClockTree::with(|clocks| {
crate::soc::clocks::configure_timg0_function_clock(
clocks,
crate::soc::clocks::Timg0FunctionClockConfig::default(),
);
crate::soc::clocks::request_timg0_function_clock(clocks);
});
cfg_if::cfg_if! {
if #[cfg(not(timergroup_default_clock_source_is_set))] {
if #[cfg(soc_has_clock_node_timg0_function_clock)] {
crate::soc::clocks::ClockTree::with(|clocks| {
crate::soc::clocks::configure_timg0_function_clock(
clocks,
crate::soc::clocks::Timg0FunctionClockConfig::default(),
);
crate::soc::clocks::request_timg0_function_clock(clocks);
});
} else if #[cfg(not(timergroup_default_clock_source_is_set))] {
// Clock source is not configurable
} else if #[cfg(soc_has_pcr)] {
crate::peripherals::PCR::regs()
@ -216,7 +218,15 @@ impl TimerGroupInstance for crate::peripherals::TIMG1<'_> {
fn configure_src_clk() {
cfg_if::cfg_if! {
if #[cfg(not(timergroup_default_clock_source_is_set))] {
if #[cfg(soc_has_clock_node_timg0_function_clock)] {
crate::soc::clocks::ClockTree::with(|clocks| {
crate::soc::clocks::configure_timg1_function_clock(
clocks,
crate::soc::clocks::Timg0FunctionClockConfig::default(),
);
crate::soc::clocks::request_timg1_function_clock(clocks);
});
} else if #[cfg(not(timergroup_default_clock_source_is_set))] {
// Clock source is not configurable
} else if #[cfg(soc_has_pcr)] {
crate::peripherals::PCR::regs()
@ -503,7 +513,9 @@ impl Timer<'_> {
fn load_value(&self, value: Duration) -> Result<(), Error> {
cfg_if::cfg_if! {
if #[cfg(esp32h2)] {
if #[cfg(soc_has_clock_node_timg0_function_clock)] {
let clk_src = Clocks::get().xtal_clock;
} else if #[cfg(esp32h2)] {
// ESP32-H2 is using PLL_48M_CLK source instead of APB_CLK
let clk_src = Clocks::get().pll_48m_clock;
} else {
@ -552,7 +564,9 @@ impl Timer<'_> {
let ticks = (value_hi << 32) | value_lo;
cfg_if::cfg_if! {
if #[cfg(esp32h2)] {
if #[cfg(soc_has_clock_node_timg0_function_clock)] {
let clk_src = Clocks::get().xtal_clock;
} else if #[cfg(esp32h2)] {
// ESP32-H2 is using PLL_48M_CLK source instead of APB_CLK
let clk_src = Clocks::get().pll_48m_clock;
} else {

2
esp-metadata-generated/src/_generated_esp32c2.rs
View File

@ -629,9 +629,9 @@ macro_rules! define_clock_tree_types {
#[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Timg0FunctionClockConfig {
#[default]
/// Selects `XTL_CLK`.
XtalClk,
#[default]
/// Selects `PLL_40M`.
Pll40m,
}

2
esp-metadata-generated/src/_generated_esp32c3.rs
View File

@ -699,9 +699,9 @@ macro_rules! define_clock_tree_types {
#[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Timg0FunctionClockConfig {
#[default]
/// Selects `XTL_CLK`.
XtalClk,
#[default]
/// Selects `APB_CLK`.
ApbClk,
}

2
esp-metadata-generated/src/_generated_esp32c6.rs
View File

@ -960,11 +960,11 @@ macro_rules! define_clock_tree_types {
#[derive(Debug, Default, Clone, Copy, PartialEq, Eq, Hash)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum Timg0FunctionClockConfig {
#[default]
/// Selects `XTAL_CLK`.
XtalClk,
/// Selects `RC_FAST_CLK`.
RcFastClk,
#[default]
/// Selects `PLL_F80M`.
PllF80m,
}

2
esp-metadata/devices/esp32c2.toml
View File

@ -178,7 +178,7 @@ clocks = { system_clocks = { clock_tree = [
{ name = "ApbSarAdc", template_params = { peripheral = "apb_saradc" } },
{ name = "UartMem", keep_enabled = true }, # TODO: keep_enabled can be removed once esp-println needs explicit initialization
{ name = "Timg0", template_params = { peripheral = "timergroup" }, keep_enabled = true, clocks = [
{ name = "FUNCTION_CLOCK", type = "mux", default = "PLL_40M", variants = [
{ name = "FUNCTION_CLOCK", type = "mux", default = "XTAL_CLK", variants = [
{ name = "XTAL_CLK", outputs = "XTL_CLK" },
{ name = "PLL_40M", outputs = "PLL_40M" },
] },

2
esp-metadata/devices/esp32c3.toml
View File

@ -188,7 +188,7 @@ clocks = { system_clocks = { clock_tree = [
{ name = "Twai0", template_params = { peripheral = "twai" } },
{ name = "Timg1", template_params = { peripheral = "timergroup1" }, clocks = "Timg0" },
{ name = "Timg0", template_params = { peripheral = "timergroup" }, keep_enabled = true, clocks = [
{ name = "FUNCTION_CLOCK", type = "mux", default = "APB_CLK", variants = [
{ name = "FUNCTION_CLOCK", type = "mux", default = "XTAL_CLK", variants = [
{ name = "XTAL_CLK", outputs = "XTL_CLK" },
{ name = "APB_CLK", outputs = "APB_CLK" },
] },

2
esp-metadata/devices/esp32c6.toml
View File

@ -232,7 +232,7 @@ clocks = { system_clocks = { clock_tree = [
{ name = "Rmt" },
{ name = "Ledc" },
{ name = "Timg0", template_params = { clk_en_template = "{{default_clk_en_template}} {{peri_clk_template}}", conf_register = "timergroup0_conf", peripheral = "tg0", peri_clk_template = "{{control}}::regs().timergroup0_timer_clk_conf().modify(|_, w| w.tg0_timer_clk_en().bit(enable));" }, keep_enabled = true, clocks = [
{ name = "FUNCTION_CLOCK", type = "mux", default = "PLL_F80M", variants = [
{ name = "FUNCTION_CLOCK", type = "mux", default = "XTAL_CLK", variants = [
{ name = "XTAL_CLK", outputs = "XTAL_CLK" },
{ name = "RC_FAST_CLK", outputs = "RC_FAST_CLK" },
{ name = "PLL_F80M", outputs = "PLL_F80M" },