2 Commits

Author SHA1 Message Date
Juraj Sadel
788d52cf69
Add app_desc to uart-interrupt example (#4477) 2025-11-11 07:01:06 +00:00
Zach Grimaldi
7fc858d836
feat: uart break send + detect (#4284)
* feat: uart break send + detect

* fix: example configs

* fix: not needed directives

* fix: instability::unstable; one line doc comment

* Update esp-hal/CHANGELOG.md

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: fold in hil test

* chore: remove old test from toml

* feat: add missing `wait_for_break` fn

* fix: self.regs

* feat: wait_for_break with timeout + async

* chore: fmt

* fix: pins now match embassy_serial example

* test: increase break length

* test: uses wait_for_break method

* test: with timeout

* fix: extend break on other test

* fix: missing assert

* test: explicit enable before first break

* test: delay after enable

* test: sync_regs on c6/h2

* test: interleaved

* test: sync and delay

* test: c6/h2 sync on send

* test: sync only without additional delay

* test: break detection amongst transmission

* fix: data tests should flush to allow full tx

* fix: delete unneeded example

* feat: added break sending to uart example

* fix: use time::Duration

* fix: TRMs dictate c3 and s3 need sync_regs after write to conf0

* fix: use Duration in HIL tests

* fix: save unoptimizable register read

* fix: remove cancellation safe (they're not)

* fix: reg assignment bits()

* test: no sync after enable_listen_rx (just after conf0 writes)

* chore: retrigger ci

* chore: retrigger ci again

* chore: update example payload to be something more relevant

* test: put back sync for c6/h2

* docs: update changelog

* docs: clarify changelog entry

* fix: missing byte in example

* fix: changelog version

* Update esp-hal/src/uart/mod.rs

Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>

---------

Co-authored-by: Dániel Buga <bugadani@gmail.com>
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
2025-11-10 08:04:34 +00:00