4 Commits

Author SHA1 Message Date
Sergio Gasquez Arcos
b5f0246129
Reordered RX-TX pairs to be consistent (#2074)
* feat: Update rx-tx order in i2s

* feat: Update rx-tx order in dma macros

* feat: Update rx-tx order in spi

* feat: Update rx-tx order in aes

* feat: Update rx-tx order in mem2mem

* feat: Update rx-tx order in twai and split methods

* feat: Update rx-tx order in twai

* feat: Update rx-tx order in twai and uart docs

* docs: Add sentence about order

* docs: Update changelog

* feat: Update rx-tx order in embassy_interrupt_spi_dma tests

* style: Rustfmt

* docs: Migrating guide

* fix: Typo

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: Diff

Co-authored-by: Dániel Buga <bugadani@gmail.com>

* fix: Tests rx-tx order

* fix: Update new_with_default_pins order

* feat: Update rx/tx order in hil_test::common_test_pins!

* feat: Update dma_extmem2mem example

* fix: Revert deleted input arg

* style: rustfmt

* feat: Disable test_asymmetric_dma_transfer for S2

---------

Co-authored-by: Dániel Buga <bugadani@gmail.com>
2024-09-06 09:56:10 +00:00
Dániel Buga
8aa1a88a23
Prefer cfg_if (#2003) 2024-08-27 11:53:55 +00:00
Dániel Buga
1003ce0c0f
Clean up SHA, RSA, mandate #[must_use] on Futures (#2000)
* Janitor go brr

* Clean up SHA

* Use max CPU speed

* RSA cleanup part 1

* Clean up nonsense comments

* Mark all futures as must_use
2024-08-27 10:43:58 +00:00
Scott Mabin
361a6c58b7
make contribution docs more visible (#1947) 2024-08-15 07:58:06 +00:00