5 Commits

Author	SHA1	Message	Date
Björn Quentin	a0ebdf0399	embassy #[main] convenience for RISC-V / Xtensa (#841)	2023-10-11 12:10:14 +01:00
Juraj Sadel	9f76798e64	Warnings cleanup and add missing PSRAM examples to the CI (#826) ... * Warnings cleanup * Add PSRAM examples to the CI	2023-09-28 08:41:55 +02:00
Jesse Braham	0064766ef2	No longer publicly expose the PeripheralClockControl struct (#817) ... * No longer publicly expose the `PeripheralClockControl` struct * Update examples as needed to get things building again * Update CHANGELOG.md * Address review feedback, fix a warning * Use a critical section for all devices other than the ESP32-C6/H2, as they modify multiple registers * Rebase and update `etm` driver to fix build errors	2023-09-26 09:07:57 -07:00
Jesse Braham	d12a3dbac5	Update all examples to remove unnecessary disabling of watchdogs (#768) ... * Update `esp32-hal` examples * Update `esp32c2-hal` examples * Update `esp32c3-hal` examples * Update `esp32c6-hal` examples * Update `esp32h2-hal` examples * Update `esp32s2-hal` examples * Update `esp32s3-hal` examples * Fix the `ram.rs` examples	2023-08-31 07:17:12 -07:00
Dániel Buga	e082d47a87	Multicore-aware executors (#723) ... * Implement multicore-aware executors * Add examples * Use pre-defined config to import SystemPeripheral * Use static_cell::make_static	2023-08-28 10:05:42 -07:00