Jesse Braham
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9bf70ff792
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Combine the esp-ulp-riscv-hal and esp32c6-lp-hal packages (#1115)
* Combine `esp-ulp-riscv-hal` and `esp32c6-lp-hal` into a single package
* Update LP core examples
* Update CI workflow
* Fix `LP_UART` example
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2024-01-26 13:46:51 +00:00 |
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Björn Quentin
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c612fecfae
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Clear LP/RTC RAM (#916)
* Clear LP_RAM/RTC RAM to make sure .bss is cleared
* Rename `ulp-riscv-hal` to `esp-ulp-riscv-hal`
* CHANGELOG.md entry
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2023-11-09 14:06:58 +01:00 |
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Björn Quentin
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47821e6b3b
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Add ULP RISC-V HAL (#840)
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2023-10-10 16:32:52 +02:00 |
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Jesse Braham
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d12a3dbac5
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Update all examples to remove unnecessary disabling of watchdogs (#768)
* Update `esp32-hal` examples
* Update `esp32c2-hal` examples
* Update `esp32c3-hal` examples
* Update `esp32c6-hal` examples
* Update `esp32h2-hal` examples
* Update `esp32s2-hal` examples
* Update `esp32s3-hal` examples
* Fix the `ram.rs` examples
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2023-08-31 07:17:12 -07:00 |
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Björn Quentin
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996da27f30
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Bare-bones support to run code on ULP-RV/LP core (#631)
* Bare-bones support to run code on ULP-RV/LP core
* Add CHANGELOG.md entry
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2023-07-03 16:15:34 +02:00 |
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