* Fix core1 startup
The original code tried to set the stack pointer and call the closure
_in the same stack frame_. This isn't possible, so the actual stack
being used was the 8K stack setup by ROM code. If this stack overflowed,
it could corrupt the ROM function .bss and .data which is why I was
seeing intermittent panic messages. I still don't understand all the
failure cases, but I know that now we are using the correct stack
properly.
* Improve multicore example
* Change log
* apply fix to esp32
* Interrupt runtime binding
* Add `set_interrupt_handler` for GPIO
* Fix
* Fix typo
* Make sure to produce a warning for an unused `#[handler]`
* Simplify GPIO interrupt handling
* Appease Clippy
* Make sure to patch the PACS in esp-hal
* Use latest PAC commit
* CHANGELOG.md entry
* Un-pin the `defmt` package's version for `esp-hal` and `esp-hal-smartled`
* Bump `esp-println` and `esp-backtrace` versions in the `examples` package
* Mention lack of MSRV guarantees when using `defmt` feature
* New package releases
* Fix the `CHANGELOG.md` check in CI
* `defmt` is annoying
* Update documentation index to point to new version, correct release date
* Remove docs.rs badge from and update docs link in `README.md`
* Silence `clippy`
* Fix documentation link in `esp-hal/README.md`
* Remove the chip-specific HAL packages
* Update some doc comments which were missed, fix build script for ESP32/S2
* Refactor/update `esp-hal-procmacros`
* Create the `examples` package, add back all of the previously existing examples
* Use `xtask` automation package for checking examples and documentation in CI
* Combine the `rt-riscv` and `rt-xtensa` features into a single `rt` feature
* Bump MSRV to 1.76.0 (shocking!)
* Re-document the features for the HAL
* No need to re-export the `riscv` package like this
* Make clippy happy, improve CI clippy checks
* Update `CHANGELOG.md`
* riscv: zero bss
Co-authored-by: Björn Quentin <bjoernQ@users.noreply.github.com>
* Address a number of review comments
* Correct pin number in `hello_rgb` example for ESP32-C3
* Address the remaining review comments
* More small tweaks/improvements
* Fix RMT examples (#11)
* Fix RMT examples
* Remove logger-init
* Make I2S examples work on ESP32 (#12)
* Make I2S examples work on ESP32
* Remove logger init
* Fix the direct-vectoring examples on all RISCV chips (#10)
* Update GPIOs for some examples...
* Embassy timer example fixes (#13)
* Switch to generic queue instead of integrated for all examples
* changelog
* Update GPIO in another example, make `rustfmt` happy
* Fix ESP32-S2 PSRAM
* Avoid UART0 and SPI flash pins (#15)
* Avoid UART0 and SPI flash pins
* Fix spi_eh1_device_loopback for non-ESP32
* Update examples/src/bin/gpio_interrupt.rs
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
---------
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
---------
Co-authored-by: Scott Mabin <scott@mabez.dev>
Co-authored-by: Björn Quentin <bjoernQ@users.noreply.github.com>
Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de>
Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
