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https://github.com/esp-rs/esp-hal.git
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9a5a546228
* esp32 & esp32s2 sharing scripts * add wokwi files * Add fixup section for esp32s2, fix ordering of sectino includes * Remove debug asm file * Use shared linker scripts for s3 with fixups * Add external.x sections back * Move ld scripts into esp-hal-common * esp32c3 unified linker scripts - rework original c3 script to use the xtensa named sections (e.g, _SECTIONNAME_start) - Add fixups in esp32c3 specific linker - Remove useless text section start and end (not required when using any form of bootloader) * Add RTC alias'. Move some shared fixups to a file * comment and cleanup * unify c2 linker script * unify c6 linker script * remove debug configs * use new esp-riscv-rt * fmt * align db symbol names * fix s3 db
33 lines
1.2 KiB
Plaintext
33 lines
1.2 KiB
Plaintext
MEMORY
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{
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/*
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https://github.com/espressif/esptool/blob/10828527038d143e049790d330ac4de76ce987d6/esptool/targets/esp32c2.py#L53-L62
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MEMORY_MAP = [[0x00000000, 0x00010000, "PADDING"],
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[0x3C000000, 0x3C400000, "DROM"],
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[0x3FCA0000, 0x3FCE0000, "DRAM"],
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[0x3FC88000, 0x3FD00000, "BYTE_ACCESSIBLE"],
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[0x3FF00000, 0x3FF50000, "DROM_MASK"],
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[0x40000000, 0x40090000, "IROM_MASK"],
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[0x42000000, 0x42400000, "IROM"],
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[0x4037C000, 0x403C0000, "IRAM"]]
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*/
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/* 272K of on soc RAM, 16K reserved for cache */
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ICACHE : ORIGIN = 0x4037C000, LENGTH = 16K
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/* Instruction RAM */
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IRAM : ORIGIN = 0x4037C000 + 16K, LENGTH = 272K - 16K
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/* Data RAM */
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DRAM : ORIGIN = 0x3FCA0000, LENGTH = 0x30000
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/* External flash */
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/* Instruction ROM */
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IROM : ORIGIN = 0x42000000 + 0x20, LENGTH = 0x200000 - 0x20
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/* Data ROM */
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DROM : ORIGIN = 0x3C000000, LENGTH = 0x200000
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}
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REGION_ALIAS("ROTEXT", IROM);
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REGION_ALIAS("RODATA", DROM);
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REGION_ALIAS("RWDATA", DRAM);
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REGION_ALIAS("RWTEXT", IRAM); |