mirror of
https://github.com/esp-rs/esp-hal.git
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03a3b6f5d6
* Update PAC to fix naming inconsistencies, simplify reset code * Update PAC and simplify * Remove mcpwm1 reset * Fix gen register name * Fixup * Finalize PAC rev
719 lines
24 KiB
Rust
719 lines
24 KiB
Rust
//! # MCPWM Operator Module
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//!
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//! ## Overview
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//! The `operator` is responsible for generating `PWM (Pulse Width Modulation)`
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//! signals and handling various aspects related to `PWM` signal generation.
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//!
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//! ## Configuration
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//! This module provides flexibility in configuring the PWM outputs. Its
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//! implementation allows for motor control and other applications that demand
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//! accurate pulse timing and sophisticated modulation techniques.
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use core::marker::PhantomData;
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use super::PeripheralGuard;
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use crate::{
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gpio::interconnect::{OutputSignal, PeripheralOutput},
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mcpwm::{PwmPeripheral, timer::Timer},
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pac,
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};
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/// Input/Output Stream descriptor for each channel
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#[derive(Copy, Clone)]
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#[allow(clippy::upper_case_acronyms, reason = "peripheral is unstable")]
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pub enum PWMStream {
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/// PWM Stream A
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PWMA,
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/// PWM Stream B
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PWMB,
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}
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/// Configuration for MCPWM Operator DeadTime
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/// It's recommended to reference the technical manual for configuration
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#[derive(Copy, Clone)]
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pub struct DeadTimeCfg {
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cfg_reg: u32,
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}
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#[allow(clippy::unusual_byte_groupings)]
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impl DeadTimeCfg {
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// NOTE: it's a bit difficult to make this typestate
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// due to the different interconnections (FED/RED vs PWMxA/PWMxB) and
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// the many modes of operation
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/// B_OUTBYPASS
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const S0: u32 = 0b01_0000_0000_0000_0000;
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/// A_OUTBYPASS
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const S1: u32 = 0b00_1000_0000_0000_0000;
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/// RED_OUTINVERT
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const S2: u32 = 0b00_0010_0000_0000_0000;
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/// FED_OUTINVERT
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const S3: u32 = 0b00_0100_0000_0000_0000;
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/// RED_INSEL
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const S4: u32 = 0b00_0000_1000_0000_0000;
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/// FED_INSEL
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const S5: u32 = 0b00_0001_0000_0000_0000;
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/// A_OUTSWAP
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const S6: u32 = 0b00_0000_0010_0000_0000;
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/// B_OUTSWAP
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const S7: u32 = 0b00_0000_0100_0000_0000;
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/// DEB_MODE
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const _S8: u32 = 0b00_0000_0001_0000_0000;
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/// Use PT_clk instead of PWM_clk
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const CLK_SEL: u32 = 0b10_0000_0000_0000_0000;
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/// Uses the following configuration:
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/// * Clock: PWM_clk
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/// * Bypass: A & B
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/// * Inputs: A->A, B->B (InSel)
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/// * Outputs: A->A, B->B (OutSwap)
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/// * No Dual-edge B
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/// * No Invert
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/// * FED/RED update mode = immediate
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pub const fn new_bypass() -> DeadTimeCfg {
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DeadTimeCfg {
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cfg_reg: Self::S0 | Self::S1,
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}
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}
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/// Active High Complementary (AHC) from Technical Reference manual
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///
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/// Will generate a PWM from input PWMA, such that output PWMA & PWMB are
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/// each others complement except during a transition in which they will
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/// be both off (as deadtime) such that they should never overlap, useful
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/// for H-Bridge type scenarios
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pub const fn new_ahc() -> DeadTimeCfg {
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DeadTimeCfg { cfg_reg: Self::S3 }
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}
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// TODO: Add some common configurations ~AHC~,ALC,AH,AC
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#[must_use]
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const fn set_flag(mut self, flag: u32, val: bool) -> Self {
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if val {
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self.cfg_reg |= flag;
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} else {
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self.cfg_reg &= !flag;
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}
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self
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}
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/// Sets FED/RED output inverter
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/// Inverts the output of the FED/RED module (excl DEB mode feedback)
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#[must_use]
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pub const fn invert_output(self, fed: bool, red: bool) -> Self {
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self.set_flag(Self::S3, fed).set_flag(Self::S2, red)
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}
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/// Swaps the output of a PWM Stream
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/// i.e. If both streams have output_swap enabled, the output of the module
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/// is swapped, while if only one is enabled that one 'copies' from the
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/// other stream
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#[must_use]
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pub const fn set_output_swap(self, stream: PWMStream, swap: bool) -> Self {
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self.set_flag(
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match stream {
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PWMStream::PWMA => Self::S6,
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PWMStream::PWMB => Self::S7,
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},
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swap,
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)
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}
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/// Set PWMA/PWMB stream to bypass everything except output_swap
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/// This means no deadtime is applied when enabled
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#[must_use]
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pub const fn set_bypass(self, stream: PWMStream, enable: bool) -> Self {
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self.set_flag(
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match stream {
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PWMStream::PWMA => Self::S1,
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PWMStream::PWMB => Self::S0,
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},
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enable,
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)
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}
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/// Select Between PWMClk & PT_Clk
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#[must_use]
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pub const fn select_clock(self, pwm_clock: bool) -> Self {
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self.set_flag(Self::CLK_SEL, pwm_clock)
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}
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/// Select which stream is used for the input of FED/RED
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#[must_use]
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pub const fn select_input(self, fed: PWMStream, red: PWMStream) -> Self {
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self.set_flag(
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Self::S5,
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match fed {
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PWMStream::PWMA => false,
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PWMStream::PWMB => true,
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},
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)
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.set_flag(
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Self::S4,
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match red {
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PWMStream::PWMA => false,
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PWMStream::PWMB => true,
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},
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)
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}
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}
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/// A MCPWM operator
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///
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/// The PWM Operator submodule has the following functions:
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/// * Generates a PWM signal pair, based on timing references obtained from the
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/// corresponding PWM timer.
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/// * Each signal out of the PWM signal pair includes a specific pattern of dead
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/// time. (Not yet implemented)
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/// * Superimposes a carrier on the PWM signal, if configured to do so. (Not yet
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/// implemented)
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/// * Handles response under fault conditions. (Not yet implemented)
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pub struct Operator<'d, const OP: u8, PWM> {
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phantom: PhantomData<&'d PWM>,
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_guard: PeripheralGuard,
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}
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impl<'d, const OP: u8, PWM: PwmPeripheral> Operator<'d, OP, PWM> {
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pub(super) fn new() -> Self {
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let guard = PeripheralGuard::new(PWM::peripheral());
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// Side note:
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// It would have been nice to deselect any timer reference on peripheral
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// initialization.
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// However experimentation (ESP32-S3) showed that writing `3` to timersel
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// will not disable the timer reference but instead act as though `2` was
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// written.
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Operator {
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phantom: PhantomData,
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_guard: guard,
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}
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}
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/// Select a [`Timer`] to be the timing reference for this operator
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///
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/// ### Note:
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/// By default TIMER0 is used
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pub fn set_timer<const TIM: u8>(&mut self, timer: &Timer<TIM, PWM>) {
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let _ = timer;
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// SAFETY:
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// We only write to our OPERATORx_TIMERSEL register
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let block = unsafe { &*PWM::block() };
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block.operator_timersel().modify(|_, w| match OP {
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0 => unsafe { w.operator0_timersel().bits(TIM) },
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1 => unsafe { w.operator1_timersel().bits(TIM) },
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2 => unsafe { w.operator2_timersel().bits(TIM) },
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_ => {
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unreachable!()
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}
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});
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}
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/// Use the A output with the given pin and configuration
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pub fn with_pin_a(
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self,
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pin: impl PeripheralOutput<'d>,
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config: PwmPinConfig<true>,
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) -> PwmPin<'d, PWM, OP, true> {
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PwmPin::new(pin, config)
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}
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/// Use the B output with the given pin and configuration
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pub fn with_pin_b(
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self,
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pin: impl PeripheralOutput<'d>,
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config: PwmPinConfig<false>,
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) -> PwmPin<'d, PWM, OP, false> {
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PwmPin::new(pin, config)
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}
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/// Use both the A and the B output with the given pins and configurations
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pub fn with_pins(
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self,
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pin_a: impl PeripheralOutput<'d>,
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config_a: PwmPinConfig<true>,
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pin_b: impl PeripheralOutput<'d>,
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config_b: PwmPinConfig<false>,
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) -> (PwmPin<'d, PWM, OP, true>, PwmPin<'d, PWM, OP, false>) {
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(PwmPin::new(pin_a, config_a), PwmPin::new(pin_b, config_b))
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}
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/// Link two pins using the deadtime generator
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///
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/// This is useful for complementary or mirrored signals with or without
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/// configured deadtime
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pub fn with_linked_pins(
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self,
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pin_a: impl PeripheralOutput<'d>,
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config_a: PwmPinConfig<true>,
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pin_b: impl PeripheralOutput<'d>,
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config_b: PwmPinConfig<false>,
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config_dt: DeadTimeCfg,
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) -> LinkedPins<'d, PWM, OP> {
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LinkedPins::new(pin_a, config_a, pin_b, config_b, config_dt)
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}
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}
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/// Configuration describing how the operator generates a signal on a connected
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/// pin
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pub struct PwmPinConfig<const IS_A: bool> {
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actions: PwmActions<IS_A>,
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update_method: PwmUpdateMethod,
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}
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impl<const IS_A: bool> PwmPinConfig<IS_A> {
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/// A configuration using [`PwmActions::UP_ACTIVE_HIGH`] and
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/// [`PwmUpdateMethod::SYNC_ON_ZERO`]
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pub const UP_ACTIVE_HIGH: Self =
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Self::new(PwmActions::UP_ACTIVE_HIGH, PwmUpdateMethod::SYNC_ON_ZERO);
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/// A configuration using [`PwmActions::UP_DOWN_ACTIVE_HIGH`] and
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/// [`PwmUpdateMethod::SYNC_ON_ZERO`]
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pub const UP_DOWN_ACTIVE_HIGH: Self = Self::new(
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PwmActions::UP_DOWN_ACTIVE_HIGH,
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PwmUpdateMethod::SYNC_ON_ZERO,
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);
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/// A configuration using [`PwmActions::empty`] and
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/// [`PwmUpdateMethod::empty`]
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pub const EMPTY: Self = Self::new(PwmActions::empty(), PwmUpdateMethod::empty());
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/// Get a configuration using the given `PwmActions` and `PwmUpdateMethod`
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pub const fn new(actions: PwmActions<IS_A>, update_method: PwmUpdateMethod) -> Self {
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PwmPinConfig {
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actions,
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update_method,
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}
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}
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}
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/// A pin driven by an MCPWM operator
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pub struct PwmPin<'d, PWM, const OP: u8, const IS_A: bool> {
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pin: OutputSignal<'d>,
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phantom: PhantomData<PWM>,
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_guard: PeripheralGuard,
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}
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impl<'d, PWM: PwmPeripheral, const OP: u8, const IS_A: bool> PwmPin<'d, PWM, OP, IS_A> {
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fn new(pin: impl PeripheralOutput<'d>, config: PwmPinConfig<IS_A>) -> Self {
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let pin = pin.into();
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let guard = PeripheralGuard::new(PWM::peripheral());
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let mut pin = PwmPin {
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pin,
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phantom: PhantomData,
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_guard: guard,
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};
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pin.set_actions(config.actions);
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pin.set_update_method(config.update_method);
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PWM::output_signal::<OP, IS_A>().connect_to(&pin.pin);
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pin.pin.set_output_enable(true);
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pin
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}
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/// Configure what actions should be taken on timing events
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pub fn set_actions(&mut self, value: PwmActions<IS_A>) {
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// SAFETY:
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// We only write to our GENx_x register
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let ch = unsafe { Self::ch() };
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let bits = value.0;
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// SAFETY:
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// `bits` is a valid bit pattern
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ch.gen_((!IS_A) as usize).write(|w| unsafe { w.bits(bits) });
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}
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/// Set how a new timestamp syncs with the timer
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pub fn set_update_method(&mut self, update_method: PwmUpdateMethod) {
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// SAFETY:
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// We only write to our GENx_x_UPMETHOD register
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let ch = unsafe { Self::ch() };
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let bits = update_method.0;
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#[cfg(esp32s3)]
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let cfg = ch.cmpr_cfg();
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#[cfg(any(esp32, esp32c6, esp32h2))]
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let cfg = ch.gen_stmp_cfg();
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cfg.modify(|_, w| unsafe {
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if IS_A {
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w.a_upmethod().bits(bits)
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} else {
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w.b_upmethod().bits(bits)
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}
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});
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}
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/// Write a new timestamp.
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/// The written value will take effect according to the set
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/// [`PwmUpdateMethod`].
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pub fn set_timestamp(&mut self, value: u16) {
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// SAFETY:
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// We only write to our GENx_TSTMP_x register
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let ch = unsafe { Self::ch() };
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#[cfg(esp32s3)]
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if IS_A {
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ch.cmpr_value0().write(|w| unsafe { w.a().bits(value) });
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} else {
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ch.cmpr_value1().write(|w| unsafe { w.b().bits(value) });
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}
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#[cfg(any(esp32, esp32c6, esp32h2))]
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if IS_A {
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ch.gen_tstmp_a().write(|w| unsafe { w.a().bits(value) });
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} else {
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ch.gen_tstmp_b().write(|w| unsafe { w.b().bits(value) });
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}
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}
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/// Get the old timestamp.
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/// The value of the timestamp will take effect according to the set
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/// [`PwmUpdateMethod`].
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pub fn timestamp(&self) -> u16 {
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// SAFETY:
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// We only read to our GENx_TSTMP_x register
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let ch = unsafe { Self::ch() };
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#[cfg(esp32s3)]
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if IS_A {
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ch.cmpr_value0().read().a().bits()
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} else {
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ch.cmpr_value1().read().b().bits()
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}
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#[cfg(any(esp32, esp32c6, esp32h2))]
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if IS_A {
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ch.gen_tstmp_a().read().a().bits()
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} else {
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ch.gen_tstmp_b().read().b().bits()
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}
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}
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/// Get the period of the timer.
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pub fn period(&self) -> u16 {
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// SAFETY:
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// We only grant access to our CFG0 register with the lifetime of &mut self
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let block = unsafe { &*PWM::block() };
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let tim_select = block.operator_timersel().read();
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let tim = match OP {
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0 => tim_select.operator0_timersel().bits(),
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1 => tim_select.operator1_timersel().bits(),
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2 => tim_select.operator2_timersel().bits(),
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_ => {
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unreachable!()
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}
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};
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// SAFETY:
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// The CFG0 registers are identical for all timers so we can pretend they're
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// TIMER0_CFG0
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block.timer(tim as usize).cfg0().read().period().bits()
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}
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unsafe fn ch() -> &'static pac::mcpwm0::CH {
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let block = unsafe { &*PWM::block() };
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block.ch(OP as usize)
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}
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}
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/// Implement no error type for the PwmPin because the method are infallible
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impl<PWM: PwmPeripheral, const OP: u8, const IS_A: bool> embedded_hal::pwm::ErrorType
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for PwmPin<'_, PWM, OP, IS_A>
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{
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type Error = core::convert::Infallible;
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}
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/// Implement the trait SetDutyCycle for PwmPin
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impl<PWM: PwmPeripheral, const OP: u8, const IS_A: bool> embedded_hal::pwm::SetDutyCycle
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for PwmPin<'_, PWM, OP, IS_A>
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{
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/// Get the max duty of the PwmPin
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fn max_duty_cycle(&self) -> u16 {
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self.period()
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}
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/// Set the max duty of the PwmPin
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fn set_duty_cycle(&mut self, duty: u16) -> Result<(), core::convert::Infallible> {
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self.set_timestamp(duty);
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Ok(())
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}
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}
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/// Two pins driven by the same timer and operator
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///
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/// Useful for complementary or mirrored signals with or without
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/// configured deadtime.
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///
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/// # H-Bridge example
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///
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/// ```rust, no_run
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#[doc = crate::before_snippet!()]
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/// # use esp_hal::mcpwm::{McPwm, PeripheralClockConfig};
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/// # use esp_hal::mcpwm::operator::{DeadTimeCfg, PwmPinConfig, PWMStream};
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/// // active high complementary using PWMA input
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/// let bridge_active = DeadTimeCfg::new_ahc();
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/// // use PWMB as input for both outputs
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/// let bridge_off = DeadTimeCfg::new_bypass().set_output_swap(PWMStream::PWMA,
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/// true);
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#[cfg_attr(
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esp32h2,
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doc = "let clock_cfg = PeripheralClockConfig::with_frequency(Rate::from_mhz(40))?;"
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)]
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#[cfg_attr(
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not(esp32h2),
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doc = "let clock_cfg = PeripheralClockConfig::with_frequency(Rate::from_mhz(32))?;"
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)]
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/// let mut mcpwm = McPwm::new(peripherals.MCPWM0, clock_cfg);
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///
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/// let mut pins = mcpwm.operator0.with_linked_pins(
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/// peripherals.GPIO0,
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/// PwmPinConfig::UP_DOWN_ACTIVE_HIGH, // use PWMA as our main input
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/// peripherals.GPIO1,
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/// PwmPinConfig::EMPTY, // keep PWMB "low"
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/// bridge_off,
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/// );
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///
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/// pins.set_falling_edge_deadtime(5);
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/// pins.set_rising_edge_deadtime(5);
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/// // pin_a: ________________________________________
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/// // pin_b: ________________________________________
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/// pins.set_timestamp_a(40); // 40% duty cycle if period configured to 100
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/// pins.set_deadtime_cfg(bridge_active);
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/// // pin_a: _______-------_____________-------______
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/// // pin_b: ------_________-----------_________-----
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/// # Ok(())
|
|
/// # }
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|
/// ```
|
|
pub struct LinkedPins<'d, PWM, const OP: u8> {
|
|
pin_a: PwmPin<'d, PWM, OP, true>,
|
|
pin_b: PwmPin<'d, PWM, OP, false>,
|
|
}
|
|
|
|
impl<'d, PWM: PwmPeripheral, const OP: u8> LinkedPins<'d, PWM, OP> {
|
|
fn new(
|
|
pin_a: impl PeripheralOutput<'d>,
|
|
config_a: PwmPinConfig<true>,
|
|
pin_b: impl PeripheralOutput<'d>,
|
|
config_b: PwmPinConfig<false>,
|
|
config_dt: DeadTimeCfg,
|
|
) -> Self {
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|
// setup deadtime config before enabling the pins
|
|
#[cfg(esp32s3)]
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|
let dt_cfg = unsafe { Self::ch() }.db_cfg();
|
|
#[cfg(not(esp32s3))]
|
|
let dt_cfg = unsafe { Self::ch() }.dt_cfg();
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|
dt_cfg.write(|w| unsafe { w.bits(config_dt.cfg_reg) });
|
|
|
|
let pin_a = PwmPin::new(pin_a, config_a);
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|
let pin_b = PwmPin::new(pin_b, config_b);
|
|
|
|
LinkedPins { pin_a, pin_b }
|
|
}
|
|
|
|
/// Configure what actions should be taken on timing events
|
|
pub fn set_actions_a(&mut self, value: PwmActions<true>) {
|
|
self.pin_a.set_actions(value)
|
|
}
|
|
/// Configure what actions should be taken on timing events
|
|
pub fn set_actions_b(&mut self, value: PwmActions<false>) {
|
|
self.pin_b.set_actions(value)
|
|
}
|
|
|
|
/// Set how a new timestamp syncs with the timer
|
|
pub fn set_update_method_a(&mut self, update_method: PwmUpdateMethod) {
|
|
self.pin_a.set_update_method(update_method)
|
|
}
|
|
/// Set how a new timestamp syncs with the timer
|
|
pub fn set_update_method_b(&mut self, update_method: PwmUpdateMethod) {
|
|
self.pin_b.set_update_method(update_method)
|
|
}
|
|
|
|
/// Write a new timestamp.
|
|
/// The written value will take effect according to the set
|
|
/// [`PwmUpdateMethod`].
|
|
pub fn set_timestamp_a(&mut self, value: u16) {
|
|
self.pin_a.set_timestamp(value)
|
|
}
|
|
/// Write a new timestamp.
|
|
/// The written value will take effect according to the set
|
|
/// [`PwmUpdateMethod`].
|
|
pub fn set_timestamp_b(&mut self, value: u16) {
|
|
self.pin_a.set_timestamp(value)
|
|
}
|
|
|
|
/// Configure the deadtime generator
|
|
pub fn set_deadtime_cfg(&mut self, config: DeadTimeCfg) {
|
|
#[cfg(esp32s3)]
|
|
let dt_cfg = unsafe { Self::ch() }.db_cfg();
|
|
#[cfg(not(esp32s3))]
|
|
let dt_cfg = unsafe { Self::ch() }.dt_cfg();
|
|
dt_cfg.write(|w| unsafe { w.bits(config.cfg_reg) });
|
|
}
|
|
|
|
/// Set the deadtime generator rising edge delay
|
|
pub fn set_rising_edge_deadtime(&mut self, dead_time: u16) {
|
|
#[cfg(esp32s3)]
|
|
let dt_red = unsafe { Self::ch() }.db_red_cfg();
|
|
#[cfg(not(esp32s3))]
|
|
let dt_red = unsafe { Self::ch() }.dt_red_cfg();
|
|
dt_red.write(|w| unsafe { w.red().bits(dead_time) });
|
|
}
|
|
/// Set the deadtime generator falling edge delay
|
|
pub fn set_falling_edge_deadtime(&mut self, dead_time: u16) {
|
|
#[cfg(esp32s3)]
|
|
let dt_fed = unsafe { Self::ch() }.db_fed_cfg();
|
|
#[cfg(not(esp32s3))]
|
|
let dt_fed = unsafe { Self::ch() }.dt_fed_cfg();
|
|
dt_fed.write(|w| unsafe { w.fed().bits(dead_time) });
|
|
}
|
|
|
|
unsafe fn ch() -> &'static pac::mcpwm0::CH {
|
|
let block = unsafe { &*PWM::block() };
|
|
block.ch(OP as usize)
|
|
}
|
|
}
|
|
|
|
/// An action the operator applies to an output
|
|
#[non_exhaustive]
|
|
#[repr(u32)]
|
|
pub enum UpdateAction {
|
|
/// Clear the output by setting it to a low level.
|
|
SetLow = 1,
|
|
/// Set the output to a high level.
|
|
SetHigh = 2,
|
|
/// Change the current output level to the opposite value.
|
|
/// If it is currently pulled high, pull it low, or vice versa.
|
|
Toggle = 3,
|
|
}
|
|
|
|
/// Settings for what actions should be taken on timing events
|
|
///
|
|
/// ### Note:
|
|
/// The hardware supports using a timestamp A event to trigger an action on
|
|
/// output B or vice versa. For clearer ownership semantics this HAL does not
|
|
/// support such configurations.
|
|
pub struct PwmActions<const IS_A: bool>(u32);
|
|
|
|
impl<const IS_A: bool> PwmActions<IS_A> {
|
|
/// Using this setting together with a timer configured with
|
|
/// [`PwmWorkingMode::Increase`](super::timer::PwmWorkingMode::Increase)
|
|
/// will set the output high for a duration proportional to the set
|
|
/// timestamp.
|
|
pub const UP_ACTIVE_HIGH: Self = Self::empty()
|
|
.on_up_counting_timer_equals_zero(UpdateAction::SetHigh)
|
|
.on_up_counting_timer_equals_timestamp(UpdateAction::SetLow);
|
|
|
|
/// Using this setting together with a timer configured with
|
|
/// [`PwmWorkingMode::UpDown`](super::timer::PwmWorkingMode::UpDown) will
|
|
/// set the output high for a duration proportional to the set
|
|
/// timestamp.
|
|
pub const UP_DOWN_ACTIVE_HIGH: Self = Self::empty()
|
|
.on_down_counting_timer_equals_timestamp(UpdateAction::SetHigh)
|
|
.on_up_counting_timer_equals_timestamp(UpdateAction::SetLow);
|
|
|
|
/// `PwmActions` with no `UpdateAction`s set
|
|
pub const fn empty() -> Self {
|
|
PwmActions(0)
|
|
}
|
|
|
|
/// Choose an `UpdateAction` for an `UTEZ` event
|
|
pub const fn on_up_counting_timer_equals_zero(self, action: UpdateAction) -> Self {
|
|
self.with_value_at_offset(action as u32, 0)
|
|
}
|
|
|
|
/// Choose an `UpdateAction` for an `UTEP` event
|
|
pub const fn on_up_counting_timer_equals_period(self, action: UpdateAction) -> Self {
|
|
self.with_value_at_offset(action as u32, 2)
|
|
}
|
|
|
|
/// Choose an `UpdateAction` for an `UTEA`/`UTEB` event
|
|
pub const fn on_up_counting_timer_equals_timestamp(self, action: UpdateAction) -> Self {
|
|
match IS_A {
|
|
true => self.with_value_at_offset(action as u32, 4),
|
|
false => self.with_value_at_offset(action as u32, 6),
|
|
}
|
|
}
|
|
|
|
/// Choose an `UpdateAction` for an `UTEA`/`UTEB` event where you can
|
|
/// specify which of the A/B to use
|
|
pub const fn on_up_counting_timer_equals_ch_timestamp<const CH_A: bool>(
|
|
self,
|
|
action: UpdateAction,
|
|
) -> Self {
|
|
match CH_A {
|
|
true => self.with_value_at_offset(action as u32, 4),
|
|
false => self.with_value_at_offset(action as u32, 6),
|
|
}
|
|
}
|
|
|
|
/// Choose an `UpdateAction` for an `DTEZ` event
|
|
pub const fn on_down_counting_timer_equals_zero(self, action: UpdateAction) -> Self {
|
|
self.with_value_at_offset(action as u32, 12)
|
|
}
|
|
|
|
/// Choose an `UpdateAction` for an `DTEP` event
|
|
pub const fn on_down_counting_timer_equals_period(self, action: UpdateAction) -> Self {
|
|
self.with_value_at_offset(action as u32, 14)
|
|
}
|
|
|
|
/// Choose an `UpdateAction` for an `DTEA`/`DTEB` event
|
|
pub const fn on_down_counting_timer_equals_timestamp(self, action: UpdateAction) -> Self {
|
|
match IS_A {
|
|
true => self.with_value_at_offset(action as u32, 16),
|
|
false => self.with_value_at_offset(action as u32, 18),
|
|
}
|
|
}
|
|
|
|
/// Choose an `UpdateAction` for an `DTEA`/`DTEB` event where you can
|
|
/// specify which of the A/B to use
|
|
pub const fn on_down_counting_timer_equals_ch_timestamp<const CH_A: bool>(
|
|
self,
|
|
action: UpdateAction,
|
|
) -> Self {
|
|
match CH_A {
|
|
true => self.with_value_at_offset(action as u32, 16),
|
|
false => self.with_value_at_offset(action as u32, 18),
|
|
}
|
|
}
|
|
|
|
const fn with_value_at_offset(self, value: u32, offset: u32) -> Self {
|
|
let mask = !(0b11 << offset);
|
|
let value = (self.0 & mask) | (value << offset);
|
|
PwmActions(value)
|
|
}
|
|
}
|
|
|
|
/// Settings for when [`PwmPin::set_timestamp`] takes effect
|
|
///
|
|
/// Multiple syncing triggers can be set.
|
|
pub struct PwmUpdateMethod(u8);
|
|
|
|
impl PwmUpdateMethod {
|
|
/// New timestamp will be applied immediately
|
|
pub const SYNC_IMMEDIATLY: Self = Self::empty();
|
|
/// New timestamp will be applied when timer is equal to zero
|
|
pub const SYNC_ON_ZERO: Self = Self::empty().sync_on_timer_equals_zero();
|
|
/// New timestamp will be applied when timer is equal to period
|
|
pub const SYNC_ON_PERIOD: Self = Self::empty().sync_on_timer_equals_period();
|
|
|
|
/// `PwmUpdateMethod` with no sync triggers.
|
|
/// Corresponds to syncing immediately
|
|
pub const fn empty() -> Self {
|
|
PwmUpdateMethod(0)
|
|
}
|
|
|
|
/// Enable syncing new timestamp values when timer is equal to zero
|
|
pub const fn sync_on_timer_equals_zero(mut self) -> Self {
|
|
self.0 |= 0b0001;
|
|
self
|
|
}
|
|
|
|
/// Enable syncing new timestamp values when timer is equal to period
|
|
pub const fn sync_on_timer_equals_period(mut self) -> Self {
|
|
self.0 |= 0b0010;
|
|
self
|
|
}
|
|
}
|