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6eca968bb8
* Add LLD option for all Xtensa chips * changelog * Fix linkerscript for esp32s3 rtc fast ram region
44 lines
1.7 KiB
Plaintext
44 lines
1.7 KiB
Plaintext
/* override entry point */
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ENTRY(ESP32Reset)
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/* reserved for ICACHE */
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RESERVE_ICACHE = 0x8000;
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VECTORS_SIZE = 0x400;
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/* Specify main memory areas
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40370000 <- IRAM/Icache -> 40378000 <- D/IRAM (I) -> 403E0000
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3FC88000 <- D/IRAM (D) -> 3FCF0000 <- DRAM/DCache -> 3FD00000
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Startup code uses the IRAM from 0x403B9000 to 0x403E0000, which is not available for static
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memory, but can only be used after app starts.
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D cache use the memory from high address, so when it's configured to 16K/32K, the region
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0x3FCF0000 ~ (3FD00000 - DATA_CACHE_SIZE) should be available. This region is not used as
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static memory, leaving to the heap.
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*/
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MEMORY
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{
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vectors_seg ( RX ) : ORIGIN = 0x40370000 + RESERVE_ICACHE, len = VECTORS_SIZE
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iram_seg ( RX ) : ORIGIN = 0x40370000 + RESERVE_ICACHE + VECTORS_SIZE, len = 328k - VECTORS_SIZE - RESERVE_ICACHE
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dram_seg ( RW ) : ORIGIN = 0x3FC88000 , len = 345856
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/* external flash
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The 0x20 offset is a convenience for the app binary image generation.
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Flash cache has 64KB pages. The .bin file which is flashed to the chip
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has a 0x18 byte file header, and each segment has a 0x08 byte segment
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header. Setting this offset makes it simple to meet the flash cache MMU's
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constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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irom_seg ( RX ) : ORIGIN = 0x42000020, len = 4M - 0x20
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drom_seg ( R ) : ORIGIN = 0x3C000020, len = 4M - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. Only for core 0 (PRO_CPU) */
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rtc_fast_seg(RWX) : ORIGIN = 0x600fe000, len = 8k
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/* RTC slow memory (data accessible). Persists over deep sleep. */
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rtc_slow_seg(RW) : ORIGIN = 0x50000000, len = 8k
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}
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