esp-hal/xtensa-lx-rt/Cargo.toml
Dániel Buga 321ae5ef1b
Rewrite Xtensa startup code in assembly (#4117)
* Initialize rtc RAM in xtensa-lx-rt

* Rewrite CPU reset handler in ASM
2025-09-17 07:57:23 +00:00

35 lines
1014 B
TOML

[package]
name = "xtensa-lx-rt"
version = "0.20.0"
edition = "2024"
rust-version = "1.88.0"
description = "Minimal startup/runtime for Xtensa LX CPUs"
documentation = "https://docs.espressif.com/projects/rust/xtensa-lx-rt/latest/"
repository = "https://github.com/esp-rs/esp-hal"
license = "MIT OR Apache-2.0"
keywords = ["lx", "peripheral", "register", "xtensa"]
categories = ["embedded", "hardware-support", "no-std"]
links = "xtensa-lx-rt"
[lib]
bench = false
test = false
[dependencies]
document-features = "0.2.11"
defmt = {version = "1.0.1", optional = true}
macros = { version = "0.4.0", package = "xtensa-lx-rt-proc-macros", path = "../xtensa-lx-rt-proc-macros" }
xtensa-lx = { version = "0.12.0", path = "../xtensa-lx" }
[build-dependencies]
[features]
## Save and restore float registers for exceptions
float-save-restore = []
## Implement `defmt::Format`
defmt = ["dep:defmt"]
[lints.rust]
unexpected_cfgs = "allow"