1789780d06
* Xtensa interrupt vectoring: peripheral source
- Initial Xtensa vectoring, updated esp32 gpio example to use new interrupt macro.
- Only peripheral sources supported.
- Only level one priority supported.
- CPU & Edge interrupts still need to be handled.
* Xtensa interrupt vectoring: CPU & EDGE
- Add support for handling CPU interrupts and edge interrupts
- PR required to xtensa-lx-rt for CPU handlers
* Xtensa interrupt vectoring: Priority
- Finally implement priortization
- Only three priorities available at the moment. Xtensa programmer guide
discourages using highpri interrupts in Rust/C. Guide also mentions
using software priortization to increase the number of Priorities
available
* support CPU interrupts, using patch xtensa-lx-rt
* Update example
* Add support & examples for the s2 & s3 too
* Fix formatting and missing imports
* Run interrupt handling in ram, optionally run the vector handler in ram in the examples
* Use xtensa_lx::Mutex CS when enabling interrupts
* Run clippy on each target
* Remove redundant features
* Fix C3 builds
* make enable unsafe. Add note about preallocated interrupts in vectored mode.
* Remove `INTERRUPT_LEVELS` static
The interrupt levels static introduces a few issues
- A lock is needed when configuring interrupts to keep
INTERRUPT_LEVELS in a consistent state
- Interrupts enabled from outside the Rust domain wouldn't be
serviced, this is the case with the wifi blobs
To remove it, the prioty configuration is now calculated dynamically in
the interrupt handler. Essentially INTERRUPT_LEVELS is now created once
the interrupt triggers. It has some benefits, such as only having to
look at interrupts configured on the current core, not both, but there
is of course an overhead with doing this in the interrupt.
* Allow raw interrupts on levels 4-7, whilst also supporting vectoring on levels 1-3
* rename core number features
* Fix examples and formatting
* use xtensa-lx-rt release, update pacs
* Support passing the trap frame into interrupt handlers
* cfg away the #[interrupt] macro when not using vectoring
* rename enable to map
move vectored feature to chip specific hals
* export vectored functions
- rename `enable_with_priority` to `enable`
- add docs for interrupt macro
* Update all examples to use vectored interrupts
esp-hal
Hardware Abstraction Layer crates for the ESP32, ESP32-C3, ESP32-S2, and ESP32-S3 from Espressif.
This project is still in the early stages of development, and as such there should be no expectation of API stability. Only a small number of peripherals currently have drivers implemented (you can see a full list here) and out of those most are still incomplete, albeit functional. These HALs are no_std; if you are looking for std support please use esp-idf-hal instead.
If you have any questions, comments, or concerns please join us on Matrix. For additional information regarding any of the crates in the monorepo, please refer to the crate's README.
| Crate | Target | Technical Reference Manual |
|---|---|---|
| esp32-hal | xtensa-esp32-none-elf |
ESP32 |
| esp32c3-hal | riscv32imc-unknown-none-elfriscv32imac-unknown-none-elf* |
ESP32-C3 |
| esp32s2-hal | xtensa-esp32s2-none-elf |
ESP32-S2 |
| esp32s3-hal | xtensa-esp32s3-none-elf |
ESP32-S3 |
* via atomic emulation
MSRV
The Minimum Supported Rust Versions are:
1.59.0for RISC-V devices (ESP32-C3)1.59.0for Xtensa devices (ESP32, ESP32-S2, ESP32-S3)
Note that targeting the Xtensa ISA requires the use of the esp-rs/rust compiler fork, whereas RISC-V is officially supported by the official Rust compiler.
License
Licensed under either of:
- Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.