mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-28 21:00:59 +00:00
a61ffef909
* Remove the `direct-vectoring` feature * Enables the feature by default * renames the old direct_vectoring enable function `enable_direct` * Make enable_direct safe, move it out of vectored module * enable interrupt preemption by default for riscv * remove pub from cpu intr handlers * add enable_direct for Xtensa too * Fix flip-link feature * Fix up interrupt docs * changelog * fix clippy suggestions * Disable P4 workflow
49 lines
1.3 KiB
TOML
49 lines
1.3 KiB
TOML
[package]
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name = "esp-riscv-rt"
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version = "0.7.0"
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edition = "2021"
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rust-version = "1.65"
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description = "Minimal runtime / startup for RISC-V CPUs from Espressif"
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repository = "https://github.com/esp-rs/esp-hal"
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license = "MIT OR Apache-2.0"
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keywords = ["esp32", "riscv", "runtime", "startup"]
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categories = ["embedded", "no-std"]
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[dependencies]
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document-features = "0.2.8"
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riscv = "0.11.1"
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riscv-rt-macros = "0.2.1"
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[features]
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## Move the stack to the start of RAM to get zero-cost stack overflow
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## protection (ESP32-C6 and ESP32-H2 only!)
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fix-sp = []
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## Indicate that the device supports `mie` and `mip` instructions.
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has-mie-mip = []
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#! ### Memory Initialization Feature Flags
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## Initialize the `data` section.
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init-data = []
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## Initialize the `.rtc_fast.data` section.
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init-rtc-fast-data = []
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## Initialize the `.rtc_fast.text` section.
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init-rtc-fast-text = []
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## Initialize the `.rwtext` section.
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init-rw-text = []
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## Zero the `.bss` section.
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zero-bss = []
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## Zero the `.rtc_fast.bss` section.
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zero-rtc-fast-bss = []
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# This feature is intended for testing; you probably don't want to enable it:
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ci = [
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"fix-sp",
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"has-mie-mip",
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"init-data",
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"init-rtc-fast-data",
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"init-rtc-fast-text",
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"init-rw-text",
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"zero-bss",
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"zero-rtc-fast-bss",
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]
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