mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-02 14:44:42 +00:00
a562863cde
* Add ROM MD5 definitions in linker and devices * Add initial MD5 support * Implement traits and add comments to MD5 module * Add MD5 example to ESP32-C3 * Test MD5 context on the quick brown fox * Implemenr From<Context> for Digest * Add MD5 to the rest of the examples * Add docs for MD5 * Remove #[repr(transparent)] from md5::Digest * Update CHANGELOG.md
37 lines
1.5 KiB
Plaintext
37 lines
1.5 KiB
Plaintext
PROVIDE(ets_delay_us = 0x40000600);
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PROVIDE(ets_update_cpu_frequency_rom = 0x40043164);
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PROVIDE(rom_i2c_writeReg = 0x40005d60);
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PROVIDE(rom_i2c_writeReg_Mask = 0x40005d6c);
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PROVIDE(rtc_get_reset_reason = 0x4000057c);
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PROVIDE(rom_config_instruction_cache_mode = 0x40001a1c);
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PROVIDE(software_reset = 0x400006d8);
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PROVIDE(software_reset_cpu = 0x400006e4);
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PROVIDE(cache_dbus_mmu_set = 0x400019b0);
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PROVIDE(ets_efuse_get_spiconfig = 0x40001f74);
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PROVIDE(esp_rom_efuse_get_flash_gpio_info = ets_efuse_get_spiconfig);
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PROVIDE(esp_rom_efuse_get_flash_wp_gpio = ets_efuse_get_wp_pad);
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PROVIDE(esp_rom_spiflash_select_qio_pins = 0x40000a68 );
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PROVIDE(esp_rom_spi_set_op_mode = 0x400008a0 );
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PROVIDE(esp_rom_spi_cmd_start = 0x40000888);
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PROVIDE(esp_rom_spi_cmd_config = 0x4000087c);
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PROVIDE(Cache_Suspend_DCache = 0x400018b4 );
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PROVIDE(Cache_Resume_DCache = 0x400018c0 );
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PROVIDE(rom_config_data_cache_mode = 0x40001a28 );
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PROVIDE(rom_config_instruction_cache_mode = 0x40001a1c );
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PROVIDE(ets_efuse_get_wp_pad = 0x40001fa4);
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PROVIDE(esp_rom_crc32_be = 0x40001ca4);
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PROVIDE(esp_rom_crc16_be = 0x40001cbc);
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PROVIDE(esp_rom_crc8_be = 0x40001cd4);
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PROVIDE(esp_rom_crc32_le = 0x40001c98);
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PROVIDE(esp_rom_crc16_le = 0x40001cb0);
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PROVIDE(esp_rom_crc8_le = 0x40001cc8);
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PROVIDE(esp_rom_md5_init = 0x40001c5c);
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PROVIDE(esp_rom_md5_update = 0x40001c68);
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PROVIDE(esp_rom_md5_final = 0x40001c74);
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PROVIDE (esp_rom_opiflash_exec_cmd = 0x400008b8);
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PROVIDE( esp_rom_spi_set_dtr_swap_mode = 0x4000093c );
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PROVIDE( esp_rom_opiflash_pin_config = 0x40000894 );
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