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* common/spi: Turn fifo size into const instead of hard-coding it into the code in various places. * common/spi: Alias `write_bytes` to `send_bytes` since they share the same interface and the same code anyway. * common/spi: Implement `read_bytes` as counterpart to `send_bytes` that is responsible only for reading bytes received via SPI. * common/spi: Rewrite `transfer` to use `send_bytes` and `read_bytes` under the hood and remove duplicate code. * common/spi: Create submodule for embedded_hal_1 that is re-exported when the `eh1` feature flag is active. This removes lots of duplicate `#[cfg(...)]` macros previously part of the code. * common/spi: Implement `SpiBus` and `SpiBusWrite` traits from the `embedded-hal 1.0.0-alpha.8`. * common/spi: Make `mosi` pin optional * esp32-hal: Add new SPI example with `eh1` traits * esp32-hal/examples/spi_eh1: Add huge transfer and bump the SPI speed to 1 MHz. * common/spi: Apply rustfmt * common/spi: Use `memcpy` to read from registers This cuts down the time between consecutive transfers from about 2 ms to less than 1 ms. * WIP: common/spi: Use `ptr::copy` to fill write FIFO cutting down the time between transfers from just below 1 ms to ~370 us. The implementation is currently broken in that it will always fill the entire FIFO from the input it is given, even if that isn't FIFO-sized... * common/spi: Add more documentation * esp32/examples/spi_eh1: Fix `transfer_in_place` * esp32/examples/spi_eh1: Add conditional compile and compile a dummy instead when the "eh1" feature isn't present. * esp32-hal: Ignore spi_eh1 example in normal builds, where the feature flag "eh1" isn't given. Building the example directly via `cargo build --example spi_eh1_loopback` will now print an error that this requires a feature flag to be active. * common/spi: Use `write_bytes` and drop `send_bytes` instead. Previoulsy, both served the same purpose, but `send_bytes` was introduced more recently and is hence less likely to cause breaking changes in existing code. * common/spi: Fix mosi pin setup * Add SPI examples with ehal 1.0.0-alpha8 traits to all targets. * common/spi: Fix `read` behavior The previous `read` implementation would only read the contents of the SPI receive FIFO and return that as data. However, the `SpiBusRead` trait defines that while reading, bytes should be written out to the bus (Because SPI is transactional, without writing nothing can be read). Reimplements the `embedded-hal` traits to correctly implement this behavior. * common/spi: Use full FIFO size on all variants All esp variants except for the esp32s2 have a 64 byte FIFO, whereas the esp32s2 has a 72 byte FIFO. * common/spi: Use common pad byte for empty writes * common/spi: Fix reading bytes from FIFO by reverting to the old method of reading 32 bytes at a time and assembling the return buffer from that. It turns out that the previous `core::slice::from_raw_parts()` doesn't work for the esp32s2 and esp32s3 variants, returning bogus data even though the correct data is present in the registers. * common/spi: Fix typos * examples: Fix spi_eh1_loopback examples
128 lines
3.7 KiB
Rust
128 lines
3.7 KiB
Rust
//! SPI loopback test
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//!
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//! Folowing pins are used:
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//! SCLK GPIO12
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//! MISO GPIO11
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//! MOSI GPIO13
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//! CS GPIO10
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//!
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//! Depending on your target and the board you are using you have to change the
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//! pins.
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//!
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//! This example transfers data via SPI.
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//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
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//! data.
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#![no_std]
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#![no_main]
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use core::fmt::Write;
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use esp32s3_hal::{
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clock::ClockControl,
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gpio::IO,
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pac::Peripherals,
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prelude::*,
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spi::{Spi, SpiMode},
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timer::TimerGroup,
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Delay,
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Rtc,
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Serial,
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};
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use panic_halt as _;
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use xtensa_lx_rt::entry;
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use embedded_hal_1::spi::blocking::SpiBus;
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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let mut system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
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// the RTC WDT, and the TIMG WDTs.
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut wdt = timer_group0.wdt;
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let mut serial0 = Serial::new(peripherals.UART0);
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wdt.disable();
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rtc.rwdt.disable();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let sclk = io.pins.gpio12;
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let miso = io.pins.gpio11;
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let mosi = io.pins.gpio13;
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let cs = io.pins.gpio10;
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let mut spi = Spi::new(
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peripherals.SPI2,
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sclk,
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mosi,
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miso,
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cs,
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1000u32.kHz(),
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SpiMode::Mode0,
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&mut system.peripheral_clock_control,
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&clocks,
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);
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let mut delay = Delay::new(&clocks);
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writeln!(serial0, "=== SPI example with embedded-hal-1 traits ===").unwrap();
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loop {
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// --- Symmetric transfer (Read as much as we write) ---
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write!(serial0, "Starting symmetric transfer...").unwrap();
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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SpiBus::transfer(&mut spi, &mut read[..], &write[..]).expect("Symmetric transfer failed");
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assert_eq!(write, read);
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writeln!(serial0, " SUCCESS").unwrap();
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delay.delay_ms(250u32);
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// --- Asymmetric transfer (Read more than we write) ---
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write!(serial0, "Starting asymetric transfer (read > write)...").unwrap();
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let mut read: [u8; 4] = [0x00; 4];
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SpiBus::transfer(&mut spi, &mut read[0..2], &write[..]).expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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writeln!(serial0, " SUCCESS").unwrap();
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delay.delay_ms(250u32);
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// --- Symmetric transfer with huge buffer ---
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// Only your RAM is the limit!
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write!(serial0, "Starting huge transfer...").unwrap();
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut read = [0x00u8; 4096];
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SpiBus::transfer(&mut spi, &mut read[..], &write[..]).expect("Huge transfer failed");
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assert_eq!(write, read);
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writeln!(serial0, " SUCCESS").unwrap();
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delay.delay_ms(250u32);
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// --- Symmetric transfer with huge buffer in-place (No additional allocation needed) ---
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write!(serial0, "Starting huge transfer (in-place)...").unwrap();
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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SpiBus::transfer_in_place(&mut spi, &mut write[..]).expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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writeln!(serial0, " SUCCESS").unwrap();
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delay.delay_ms(250u32);
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}
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}
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