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https://github.com/esp-rs/esp-hal.git
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* Check for ST_TOUT / MAIN_ST_TOUT * Fix & CHANGELOG * cfg gate * Field renaming in PACs * Introduce FsmTimeout type * `new_const` * Review comments * Async I2C tests * Remove FSM timeout for S2 * Add test * Don't run `async_test_timeout_when_scl_kept_low` on S2 - we know it fails * Fix --------- Co-authored-by: Scott Mabin <scott@mabez.dev>
210 lines
6.1 KiB
Rust
210 lines
6.1 KiB
Rust
//! I2C test
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: unstable embassy
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#![no_std]
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#![no_main]
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use esp_hal::{
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Async,
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Blocking,
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i2c::master::{AcknowledgeCheckFailedReason, Config, Error, I2c, I2cAddress, Operation},
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};
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use hil_test as _;
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struct Context {
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i2c: I2c<'static, Blocking>,
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}
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fn _async_driver_is_compatible_with_blocking_ehal() {
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fn _with_driver(driver: I2c<'static, Async>) {
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_with_ehal(driver);
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}
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fn _with_ehal(_: impl embedded_hal::i2c::I2c) {}
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}
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const DUT_ADDRESS: u8 = 0x77;
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const NON_EXISTENT_ADDRESS: u8 = 0x6b;
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#[cfg(test)]
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#[embedded_test::tests(default_timeout = 3, executor = hil_test::Executor::new())]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let (sda, scl) = hil_test::i2c_pins!(peripherals);
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// Create a new peripheral object with the described wiring and standard
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// I2C clock speed:
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let i2c = I2c::new(peripherals.I2C0, Config::default())
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.unwrap()
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.with_sda(sda)
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.with_scl(scl);
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Context { i2c }
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}
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#[test]
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fn invalid_address_returns_error(mut ctx: Context) {
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assert_eq!(
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ctx.i2c.write(0x80, &[]),
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Err(Error::AddressInvalid(I2cAddress::SevenBit(0x80)))
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);
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assert_eq!(
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ctx.i2c.read(0x80, &mut [0; 1]),
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Err(Error::AddressInvalid(I2cAddress::SevenBit(0x80)))
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);
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assert_eq!(
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ctx.i2c.write_read(0x80, &[0x77], &mut [0; 1]),
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Err(Error::AddressInvalid(I2cAddress::SevenBit(0x80)))
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);
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}
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#[test]
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fn empty_write_returns_ack_error_for_unknown_address(mut ctx: Context) {
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// on some chips we can determine the ack-check-failed reason but not on all
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// chips
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cfg_if::cfg_if! {
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if #[cfg(any(esp32,esp32s2,esp32c2,esp32c3))] {
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assert_eq!(
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ctx.i2c.write(NON_EXISTENT_ADDRESS, &[]),
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Err(Error::AcknowledgeCheckFailed(
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AcknowledgeCheckFailedReason::Unknown
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))
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);
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} else {
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assert_eq!(
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ctx.i2c.write(NON_EXISTENT_ADDRESS, &[]),
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Err(Error::AcknowledgeCheckFailed(
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AcknowledgeCheckFailedReason::Address
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))
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);
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}
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}
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assert_eq!(ctx.i2c.write(DUT_ADDRESS, &[]), Ok(()));
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}
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#[test]
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fn test_read_cali(mut ctx: Context) {
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let mut read_data = [0u8; 22];
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// have a failing read which might could leave the peripheral in an undesirable
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// state
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ctx.i2c
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.write_read(NON_EXISTENT_ADDRESS, &[0xaa], &mut read_data)
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.ok();
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// do the real read which should succeed
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ctx.i2c
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.write_read(DUT_ADDRESS, &[0xaa], &mut read_data)
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.ok();
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assert_ne!(read_data, [0u8; 22])
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}
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#[test]
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fn test_read_cali_with_transactions(mut ctx: Context) {
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let mut read_data = [0u8; 22];
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// do the real read which should succeed
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ctx.i2c
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.transaction(
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DUT_ADDRESS,
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&mut [Operation::Write(&[0xaa]), Operation::Read(&mut read_data)],
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)
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.ok();
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assert_ne!(read_data, [0u8; 22])
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}
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#[test]
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async fn async_empty_write_returns_ack_error_for_unknown_address(ctx: Context) {
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let mut i2c = ctx.i2c.into_async();
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// on some chips we can determine the ack-check-failed reason but not on all
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// chips
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cfg_if::cfg_if! {
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if #[cfg(any(esp32,esp32s2,esp32c2,esp32c3))] {
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assert_eq!(
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i2c.write_async(NON_EXISTENT_ADDRESS, &[]).await,
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Err(Error::AcknowledgeCheckFailed(
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AcknowledgeCheckFailedReason::Unknown
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))
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);
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} else {
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assert_eq!(
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i2c.write_async(NON_EXISTENT_ADDRESS, &[]).await,
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Err(Error::AcknowledgeCheckFailed(
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AcknowledgeCheckFailedReason::Address
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))
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);
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}
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}
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assert_eq!(i2c.write_async(DUT_ADDRESS, &[]).await, Ok(()));
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}
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#[test]
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async fn async_test_read_cali(ctx: Context) {
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let mut i2c = ctx.i2c.into_async();
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let mut read_data = [0u8; 22];
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// have a failing read which might could leave the peripheral in an undesirable
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// state
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i2c.write_read_async(NON_EXISTENT_ADDRESS, &[0xaa], &mut read_data)
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.await
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.ok();
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// do the real read which should succeed
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i2c.write_read_async(DUT_ADDRESS, &[0xaa], &mut read_data)
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.await
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.ok();
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assert_ne!(read_data, [0u8; 22])
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}
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#[test]
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async fn async_test_read_cali_with_transactions(ctx: Context) {
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let mut i2c = ctx.i2c.into_async();
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let mut read_data = [0u8; 22];
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// do the real read which should succeed
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i2c.transaction_async(
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DUT_ADDRESS,
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&mut [Operation::Write(&[0xaa]), Operation::Read(&mut read_data)],
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)
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.await
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.ok();
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assert_ne!(read_data, [0u8; 22])
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}
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// This is still an issue on ESP32-S2
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#[cfg(not(esp32s2))]
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#[test]
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async fn async_test_timeout_when_scl_kept_low(_ctx: Context) {
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let mut i2c = I2c::new(
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unsafe { esp_hal::peripherals::I2C0::steal() },
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Config::default(),
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)
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.unwrap()
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.with_sda(unsafe { esp_hal::peripherals::GPIO4::steal() })
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.with_scl(unsafe { esp_hal::peripherals::GPIO5::steal() })
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.into_async();
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esp_hal::gpio::InputSignal::I2CEXT0_SCL.connect_to(&esp_hal::gpio::Level::Low);
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let mut read_data = [0u8; 22];
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// will run into an error but it should return at least
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i2c.write_read_async(DUT_ADDRESS, &[0xaa], &mut read_data)
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.await
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.ok();
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}
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}
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