mirror of
https://github.com/esp-rs/esp-hal.git
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* remove async features * phy-usb config * modem powersaving * Fix examples * make ps a runtime config * fix linting * changelog and migration guide * revert esp-config changes * remove blanklines after doc comments * cfg away ps API
141 lines
4.4 KiB
Rust
141 lines
4.4 KiB
Rust
// use atomic_polyfill::AtomicU32;
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use portable_atomic::{AtomicU32, Ordering};
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use super::phy_init_data::PHY_INIT_DATA_DEFAULT;
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use crate::{
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binary::include::*,
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compat::common::str_from_c,
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hal::system::{RadioClockController, RadioPeripherals},
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};
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const SOC_PHY_DIG_REGS_MEM_SIZE: usize = 21 * 4;
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static mut SOC_PHY_DIG_REGS_MEM: [u8; SOC_PHY_DIG_REGS_MEM_SIZE] = [0u8; SOC_PHY_DIG_REGS_MEM_SIZE];
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static mut G_IS_PHY_CALIBRATED: bool = false;
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static mut G_PHY_DIGITAL_REGS_MEM: *mut u32 = core::ptr::null_mut();
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static mut S_IS_PHY_REG_STORED: bool = false;
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static PHY_ACCESS_REF: AtomicU32 = AtomicU32::new(0);
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pub(crate) fn enable_wifi_power_domain() {
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// In esp-idf, SOC_PMU_SUPPORTED is set which makes
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// `esp_wifi_bt_power_domain_on` a no-op.
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}
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pub(crate) fn phy_mem_init() {
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unsafe {
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G_PHY_DIGITAL_REGS_MEM = core::ptr::addr_of_mut!(SOC_PHY_DIG_REGS_MEM).cast();
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}
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}
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pub(crate) unsafe fn phy_enable() {
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let count = PHY_ACCESS_REF.fetch_add(1, Ordering::SeqCst);
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if count == 0 {
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critical_section::with(|_| {
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phy_enable_clock();
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if !G_IS_PHY_CALIBRATED {
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let mut cal_data: [u8; core::mem::size_of::<esp_phy_calibration_data_t>()] =
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[0u8; core::mem::size_of::<esp_phy_calibration_data_t>()];
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let phy_version = get_phy_version_str();
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trace!("phy_version {}", str_from_c(phy_version as *const u8));
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let init_data = &PHY_INIT_DATA_DEFAULT;
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// this would cause linker errors when the feature is activated - see https://github.com/esp-rs/esp-wifi/issues/457
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// #[cfg(phy_enable_usb)]
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// {
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// extern "C" {
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// pub fn phy_bbpll_en_usb(param: bool);
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// }
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// phy_bbpll_en_usb(true);
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// }
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register_chipv7_phy(
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init_data,
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&mut cal_data as *mut _
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as *mut crate::binary::include::esp_phy_calibration_data_t,
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esp_phy_calibration_mode_t_PHY_RF_CAL_FULL,
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);
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G_IS_PHY_CALIBRATED = true;
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} else {
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phy_wakeup_init();
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phy_digital_regs_load();
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}
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#[cfg(feature = "ble")]
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{
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extern "C" {
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fn coex_pti_v2();
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}
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coex_pti_v2();
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}
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trace!("PHY ENABLE");
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});
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}
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}
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#[allow(unused)]
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pub(crate) unsafe fn phy_disable() {
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let count = PHY_ACCESS_REF.fetch_sub(1, Ordering::SeqCst);
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if count == 1 {
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critical_section::with(|_| {
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phy_digital_regs_store();
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// Disable PHY and RF.
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phy_close_rf();
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// Disable PHY temperature sensor
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phy_xpd_tsens();
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// #if CONFIG_IDF_TARGET_ESP32
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// // Update WiFi MAC time before disalbe WiFi/BT common peripheral
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// clock phy_update_wifi_mac_time(true,
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// esp_timer_get_time()); #endif
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// Disable WiFi/BT common peripheral clock. Do not disable clock for hardware
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// RNG
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phy_disable_clock();
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trace!("PHY DISABLE");
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});
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}
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}
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fn phy_digital_regs_load() {
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unsafe {
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if S_IS_PHY_REG_STORED && !G_PHY_DIGITAL_REGS_MEM.is_null() {
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phy_dig_reg_backup(false, G_PHY_DIGITAL_REGS_MEM);
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}
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}
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}
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fn phy_digital_regs_store() {
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unsafe {
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if !G_PHY_DIGITAL_REGS_MEM.is_null() {
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phy_dig_reg_backup(true, G_PHY_DIGITAL_REGS_MEM);
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S_IS_PHY_REG_STORED = true;
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}
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}
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}
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pub(crate) unsafe fn phy_enable_clock() {
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trace!("phy_enable_clock");
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// stealing RADIO_CLK is safe since it is passed (as mutable reference or by
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// value) into `init`
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let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() };
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radio_clocks.enable(RadioPeripherals::Phy);
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trace!("phy_enable_clock done!");
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}
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#[allow(unused)]
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pub(crate) unsafe fn phy_disable_clock() {
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trace!("phy_disable_clock");
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// stealing RADIO_CLK is safe since it is passed (as mutable reference or by
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// value) into `init`
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let mut radio_clocks = unsafe { esp_hal::peripherals::RADIO_CLK::steal() };
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radio_clocks.disable(RadioPeripherals::Phy);
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trace!("phy_disable_clock done!");
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}
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