esp-hal/xtensa-lx-rt/xtensa.in.x
Dániel Buga 321ae5ef1b
Rewrite Xtensa startup code in assembly (#4117)
* Initialize rtc RAM in xtensa-lx-rt

* Rewrite CPU reset handler in ASM
2025-09-17 07:57:23 +00:00

81 lines
1.5 KiB
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/* before memory.x to allow override */
ENTRY(Reset)
INCLUDE memory.x
/* after memory.x to allow override */
PROVIDE(__pre_init = no_init_hook);
PROVIDE(__zero_bss = default_mem_hook);
PROVIDE(__init_data = default_mem_hook);
PROVIDE(__init_persistent = default_mem_hook);
PROVIDE(__post_init = no_init_hook);
INCLUDE exception.x
SECTIONS {
.text : ALIGN(4)
{
_stext = .;
. = ALIGN (4);
_text_start = ABSOLUTE(.);
. = ALIGN (4);
*(.literal .text .literal.* .text.*)
_text_end = ABSOLUTE(.);
_etext = .;
} > ROTEXT
.rodata : ALIGN(4)
{
_rodata_start = ABSOLUTE(.);
. = ALIGN (4);
*(.rodata .rodata.*)
_rodata_end = ABSOLUTE(.);
} > RODATA
.data : ALIGN(4)
{
_data_start = ABSOLUTE(.);
. = ALIGN (4);
*(.data .data.*)
_data_end = ABSOLUTE(.);
} > RWDATA AT > RODATA
/* LMA of .data */
_sidata = LOADADDR(.data);
.bss (NOLOAD) : ALIGN(4)
{
_bss_start = ABSOLUTE(.);
. = ALIGN (4);
*(.bss .bss.* COMMON)
_bss_end = ABSOLUTE(.);
} > RWDATA
.noinit (NOLOAD) : ALIGN(4)
{
. = ALIGN(4);
*(.noinit .noinit.*)
} > RWDATA
.rwtext : ALIGN(4)
{
. = ALIGN (4);
*(.rwtext.literal .rwtext .rwtext.literal.* .rwtext.*)
} > RWTEXT
/* must be last segment using RWTEXT */
.text_heap_start (NOLOAD) : ALIGN(4)
{
. = ALIGN (4);
_text_heap_start = ABSOLUTE(.);
} > RWTEXT
/* must be last segment using RWDATA */
.heap_start (NOLOAD) : ALIGN(4)
{
. = ALIGN (4);
_heap_start = ABSOLUTE(.);
} > RWDATA
}