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517b5ccbe2
* Make cargo xfmt respect the format config * Make sure comments and doc code have the same width
675 lines
23 KiB
Rust
675 lines
23 KiB
Rust
//! # PSRAM "virtual peripheral" driver (ESP32-S2)
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//!
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//! ## Overview
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//!
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//! The `PSRAM` module provides support for accessing and controlling the
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//! `Pseudo Static Random Access Memory (PSRAM)` on the `ESP32-S2`.
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//!
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//! The `PSRAM` module enables users to interface with the `PSRAM` memory
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//! present on the `ESP32-S2` chip. `PSRAM` provides additional external memory
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//! to supplement the internal memory of the `ESP32-S2`, allowing for increased
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//! storage capacity and improved performance in certain applications.
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//!
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//! //! ## Examples
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//!
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//! ### Quad PSRAM
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//! This example shows how to use PSRAM as heap-memory via esp-alloc.
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//! You need an ESP32S2 with at least 2 MB of PSRAM memory.
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//! Notice that PSRAM example **must** be built in release mode!
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//!
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//! ```rust, no_run
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#![doc = crate::before_snippet!()]
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//! # extern crate alloc;
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//! # use alloc::{string::String, vec::Vec};
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//! # use esp_alloc as _;
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//! # use esp_hal::psram;
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//!
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//! // Initialize PSRAM and add it as a heap memory region
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//! fn init_psram_heap(start: *mut u8, size: usize) {
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//! unsafe {
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//! esp_alloc::HEAP.add_region(esp_alloc::HeapRegion::new(
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//! start,
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//! size,
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//! esp_alloc::MemoryCapability::External.into(),
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//! ));
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//! }
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//! }
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//!
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//! // Initialize PSRAM and add it to the heap
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//! let (start, size) = psram::init_psram(peripherals.PSRAM,
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//! psram::PsramConfig::default());
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//!
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//! init_psram_heap(start, size);
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//!
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//! let mut large_vec: Vec<u32> = Vec::with_capacity(500 * 1024 / 4);
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//!
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//! for i in 0..(500 * 1024 / 4) {
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//! large_vec.push((i & 0xff) as u32);
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//! }
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//!
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//! let string = String::from("A string allocated in PSRAM");
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//! # }
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//! ```
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use crate::peripherals::{EXTMEM, SPI0, SPI1};
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pub use crate::soc::psram_common::*;
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const EXTMEM_ORIGIN: usize = 0x3f500000;
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// Cache Speed
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#[derive(PartialEq, Eq, Debug, Copy, Clone, Default)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[allow(missing_docs)]
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pub enum PsramCacheSpeed {
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PsramCacheS80m = 1,
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PsramCacheS40m,
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PsramCacheS26m,
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PsramCacheS20m,
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#[default]
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PsramCacheMax,
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}
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/// PSRAM configuration
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#[derive(Copy, Clone, Debug, Default)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub struct PsramConfig {
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/// PSRAM size
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pub size: PsramSize,
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/// Cache Speed
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pub speed: PsramCacheSpeed,
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}
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/// Initialize PSRAM to be used for data.
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///
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/// Returns the start of the mapped memory and the size
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#[procmacros::ram]
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pub(crate) fn init_psram(config: PsramConfig) {
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let mut config = config;
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utils::psram_init(&mut config);
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#[allow(unused)]
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enum CacheLayout {
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Invalid = 0,
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ICacheLow = 1 << 0,
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ICacheHigh = 1 << 1,
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DCacheLow = 1 << 2,
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DCacheHigh = 1 << 3,
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}
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const MMU_ACCESS_SPIRAM: u32 = 1 << 16;
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const CACHE_SIZE_8KB: u32 = 0;
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const CACHE_4WAYS_ASSOC: u32 = 0;
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const CACHE_LINE_SIZE_16B: u32 = 0;
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unsafe extern "C" {
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/// Allocate memory to used by ICache and DCache.
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///
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/// [`sram0_layout`]: u32 the usage of first 8KB internal memory block,
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/// can be CACHE_MEMORY_INVALID,
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/// CACHE_MEMORY_ICACHE_LOW,
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/// CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW and
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/// CACHE_MEMORY_DCACHE_HIGH
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/// [`sram1_layout`]: the usage of second 8KB internal memory block,
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/// [`sram2_layout`]: the usage of third 8KB internal memory block
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/// [`sram3_layout`]: the usage of forth 8KB internal memory block
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fn Cache_Allocate_SRAM(
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sram0_layout: u32,
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sram1_layout: u32,
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sram2_layout: u32,
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sram3_layout: u32,
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);
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/// Set DCache mmu mapping.
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///
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/// [`ext_ram`]: u32 DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid.
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/// [`vaddr`]: u32 Virtual address in CPU address space.
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/// [`paddr`]: u32 Physical address in external memory. Should be aligned by psize.
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/// [`psize`]: u32 Page size of DCache, in kilobytes. Should be 64 here.
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/// [`num`]: u32 Pages to be set.
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/// [`fixes`]: u32 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page.
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fn cache_dbus_mmu_set(
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ext_ram: u32,
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vaddr: u32,
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paddr: u32,
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psize: u32,
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num: u32,
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fixed: u32,
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) -> i32;
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/// Set DCache modes: cache size, associate ways and cache line size.
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///
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/// [`cache_size`]: u32 the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL
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/// [`ways`]: u32 the associate ways of cache, can only be CACHE_4WAYS_ASSOC
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/// [`cache_line_size`]: u32 the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B
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fn Cache_Set_DCache_Mode(cache_size: u32, ways: u32, cache_line_size: u32);
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/// Invalidate all cache items in DCache.
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fn Cache_Invalidate_DCache_All();
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}
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unsafe {
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Cache_Allocate_SRAM(
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CacheLayout::ICacheLow as u32,
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CacheLayout::DCacheLow as u32,
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CacheLayout::Invalid as u32,
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CacheLayout::Invalid as u32,
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);
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Cache_Set_DCache_Mode(CACHE_SIZE_8KB, CACHE_4WAYS_ASSOC, CACHE_LINE_SIZE_16B);
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Cache_Invalidate_DCache_All();
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const START_PAGE: u32 = 0;
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if cache_dbus_mmu_set(
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MMU_ACCESS_SPIRAM,
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EXTMEM_ORIGIN as u32,
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START_PAGE << 16,
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64,
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config.size.get() as u32 / 1024 / 64, // number of pages to map
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0,
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) != 0
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{
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panic!("cache_dbus_mmu_set failed");
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}
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EXTMEM::regs().pro_dcache_ctrl1().modify(|_, w| {
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w.pro_dcache_mask_bus0().clear_bit();
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w.pro_dcache_mask_bus1().clear_bit();
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w.pro_dcache_mask_bus2().clear_bit()
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});
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}
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unsafe {
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crate::soc::MAPPED_PSRAM.memory_range = EXTMEM_ORIGIN..EXTMEM_ORIGIN + config.size.get();
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}
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}
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pub(crate) mod utils {
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use super::*;
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const PSRAM_RESET_EN: u16 = 0x66;
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const PSRAM_RESET: u16 = 0x99;
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const PSRAM_DEVICE_ID: u16 = 0x9F;
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const CS_PSRAM_SEL: u8 = 1 << 1;
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/// PS-RAM addressing mode
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#[derive(PartialEq, Eq, Debug, Copy, Clone, Default)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[allow(unused)]
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pub enum PsramVaddrMode {
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/// App and pro CPU use their own flash cache for external RAM access
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#[default]
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Normal = 0,
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/// App and pro CPU share external RAM caches: pro CPU has low2M, app
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/// CPU has high 2M
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Lowhigh,
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/// App and pro CPU share external RAM caches: pro CPU does even 32yte
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/// ranges, app does odd ones.
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Evenodd,
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}
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// Function initializes the PSRAM by configuring GPIO pins, resetting the PSRAM,
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// and enabling Quad I/O (QIO) mode. It also calls the psram_cache_init
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// function to configure cache parameters and read/write commands.
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pub(crate) fn psram_init(config: &mut PsramConfig) {
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psram_gpio_config();
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if config.size.is_auto() {
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psram_disable_qio_mode();
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// read chip id
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let mut dev_id = 0u32;
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psram_exec_cmd(
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CommandMode::PsramCmdSpi,
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PSRAM_DEVICE_ID,
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8, // command and command bit len
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0,
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24, // address and address bit len
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0, // dummy bit len
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core::ptr::null(),
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0, // tx data and tx bit len
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&mut dev_id as *mut _ as *mut u8,
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24, // rx data and rx bit len
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CS_PSRAM_SEL, // cs bit mask
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false,
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);
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info!("chip id = {:x}", dev_id);
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let size = if dev_id != 0xffffff {
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const PSRAM_ID_EID_S: u32 = 16;
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const PSRAM_ID_EID_M: u32 = 0xff;
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const PSRAM_EID_SIZE_M: u32 = 0x07;
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const PSRAM_EID_SIZE_S: u32 = 5;
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let size_id = (((dev_id >> PSRAM_ID_EID_S) & PSRAM_ID_EID_M) >> PSRAM_EID_SIZE_S)
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& PSRAM_EID_SIZE_M;
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const PSRAM_EID_SIZE_32MBITS: u32 = 1;
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const PSRAM_EID_SIZE_64MBITS: u32 = 2;
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match size_id {
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PSRAM_EID_SIZE_64MBITS => 8 * 1024 * 1024,
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PSRAM_EID_SIZE_32MBITS => 4 * 1024 * 1024,
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_ => 2 * 1024 * 1024,
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}
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} else {
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0
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};
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info!("size is {}", size);
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config.size = PsramSize::Size(size);
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}
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psram_reset_mode();
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psram_enable_qio_mode();
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psram_cache_init(config.speed, PsramVaddrMode::Normal);
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}
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// send reset command to psram, in spi mode
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fn psram_reset_mode() {
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psram_exec_cmd(
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CommandMode::PsramCmdSpi,
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PSRAM_RESET_EN,
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8, // command and command bit len
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0,
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0, // address and address bit len
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0, // dummy bit len
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core::ptr::null(),
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0, // tx data and tx bit len
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core::ptr::null_mut(),
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0, // rx data and rx bit len
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CS_PSRAM_SEL, // cs bit mask
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false,
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); // whether is program/erase operation
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psram_exec_cmd(
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CommandMode::PsramCmdSpi,
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PSRAM_RESET,
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8, // command and command bit len
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0,
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0, // address and address bit len
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0, // dummy bit len
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core::ptr::null(),
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0, // tx data and tx bit len
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core::ptr::null_mut(),
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0, // rx data and rx bit len
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CS_PSRAM_SEL, // cs bit mask
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false,
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); // whether is program/erase operation
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}
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/// Enter QPI mode
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fn psram_enable_qio_mode() {
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const PSRAM_ENTER_QMODE: u16 = 0x35;
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const CS_PSRAM_SEL: u8 = 1 << 1;
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psram_exec_cmd(
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CommandMode::PsramCmdSpi,
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PSRAM_ENTER_QMODE,
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8, // command and command bit len
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0,
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0, // address and address bit len
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0, // dummy bit len
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core::ptr::null(),
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0, // tx data and tx bit len
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core::ptr::null_mut(),
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0, // rx data and rx bit len
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CS_PSRAM_SEL, // cs bit mask
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false, // whether is program/erase operation
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);
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}
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/// Exit QPI mode
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fn psram_disable_qio_mode() {
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const PSRAM_EXIT_QMODE: u16 = 0xF5;
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const CS_PSRAM_SEL: u8 = 1 << 1;
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psram_exec_cmd(
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CommandMode::PsramCmdQpi,
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PSRAM_EXIT_QMODE,
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8, // command and command bit len
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0,
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0, // address and address bit len
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0, // dummy bit len
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core::ptr::null(),
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0, // tx data and tx bit len
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core::ptr::null_mut(),
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0, // rx data and rx bit len
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CS_PSRAM_SEL, // cs bit mask
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false, // whether is program/erase operation
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);
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}
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#[derive(PartialEq)]
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#[allow(unused)]
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enum CommandMode {
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PsramCmdQpi = 0,
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PsramCmdSpi = 1,
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}
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#[allow(clippy::too_many_arguments)]
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#[inline(always)]
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fn psram_exec_cmd(
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mode: CommandMode,
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cmd: u16,
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cmd_bit_len: u16,
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addr: u32,
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addr_bit_len: u32,
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dummy_bits: u32,
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mosi_data: *const u8,
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mosi_bit_len: u32,
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miso_data: *mut u8,
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miso_bit_len: u32,
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cs_mask: u8,
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is_write_erase_operation: bool,
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) {
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unsafe extern "C" {
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/// Start a spi user command sequence
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/// [`spi_num`] spi port
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/// [`rx_buf`] buffer pointer to receive data
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/// [`rx_len`] receive data length in byte
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/// [`cs_en_mask`] decide which cs to use, 0 for cs0, 1 for cs1
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/// [`is_write_erase`] to indicate whether this is a write or erase
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/// operation, since the CPU would check permission
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fn esp_rom_spi_cmd_start(
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spi_num: u32,
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rx_buf: *const u8,
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rx_len: u16,
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cs_en_mask: u8,
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is_write_erase: bool,
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);
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}
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unsafe {
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let spi1 = SPI1::regs();
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let backup_usr = spi1.user().read().bits();
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let backup_usr1 = spi1.user1().read().bits();
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let backup_usr2 = spi1.user2().read().bits();
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let backup_ctrl = spi1.ctrl().read().bits();
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psram_set_op_mode(mode);
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_psram_exec_cmd(
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cmd,
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cmd_bit_len,
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&addr,
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addr_bit_len,
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dummy_bits,
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mosi_data,
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mosi_bit_len,
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miso_data,
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miso_bit_len,
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);
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esp_rom_spi_cmd_start(
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1,
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miso_data,
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(miso_bit_len / 8) as u16,
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cs_mask,
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is_write_erase_operation,
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);
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spi1.user().write(|w| w.bits(backup_usr));
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spi1.user1().write(|w| w.bits(backup_usr1));
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spi1.user2().write(|w| w.bits(backup_usr2));
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spi1.ctrl().write(|w| w.bits(backup_ctrl));
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}
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}
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#[allow(clippy::too_many_arguments)]
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#[inline(always)]
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fn _psram_exec_cmd(
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cmd: u16,
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cmd_bit_len: u16,
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addr: *const u32,
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addr_bit_len: u32,
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dummy_bits: u32,
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mosi_data: *const u8,
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mosi_bit_len: u32,
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miso_data: *mut u8,
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miso_bit_len: u32,
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) {
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#[repr(C)]
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#[allow(non_camel_case_types)]
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struct esp_rom_spi_cmd_t {
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cmd: u16, // Command value
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cmd_bit_len: u16, // Command byte length
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addr: *const u32, // Point to address value
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addr_bit_len: u32, // Address byte length
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tx_data: *const u32, // Point to send data buffer
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tx_data_bit_len: u32, // Send data byte length.
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rx_data: *mut u32, // Point to recevie data buffer
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rx_data_bit_len: u32, // Recevie Data byte length.
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dummy_bit_len: u32,
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}
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unsafe extern "C" {
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/// Config the spi user command
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/// [`spi_num`] spi port
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/// [`pcmd`] pointer to accept the spi command struct
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fn esp_rom_spi_cmd_config(spi_num: u32, pcmd: *const esp_rom_spi_cmd_t);
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}
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let conf = esp_rom_spi_cmd_t {
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cmd,
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cmd_bit_len,
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addr,
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addr_bit_len,
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tx_data: mosi_data as *const u32,
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tx_data_bit_len: mosi_bit_len,
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rx_data: miso_data as *mut u32,
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rx_data_bit_len: miso_bit_len,
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dummy_bit_len: dummy_bits,
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};
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unsafe {
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esp_rom_spi_cmd_config(1, &conf);
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}
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}
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fn psram_set_op_mode(mode: CommandMode) {
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unsafe extern "C" {
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fn esp_rom_spi_set_op_mode(spi: u32, mode: u32);
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}
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const ESP_ROM_SPIFLASH_QIO_MODE: u32 = 0;
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const ESP_ROM_SPIFLASH_SLOWRD_MODE: u32 = 5;
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unsafe {
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match mode {
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CommandMode::PsramCmdQpi => {
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esp_rom_spi_set_op_mode(1, ESP_ROM_SPIFLASH_QIO_MODE);
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// this should be `fcmd_quad` - apparently our ESP32-S2 SVD isn't correct for
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// SPI1 and SPI0. i.e. GP-SPI vs MEM-SPI
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//
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// TODO fix the SVD and change this back!
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// (i.e. in our SVD FCMD_QUAD is bit 9 while it should be bit 8)
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SPI1::regs().ctrl().modify(|_, w| w.fcmd_dual().set_bit());
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}
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CommandMode::PsramCmdSpi => {
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esp_rom_spi_set_op_mode(1, ESP_ROM_SPIFLASH_SLOWRD_MODE);
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|
}
|
|
}
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|
}
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|
}
|
|
|
|
#[repr(C)]
|
|
struct PsRamIo {
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|
flash_clk_io: u8,
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|
flash_cs_io: u8,
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|
psram_clk_io: u8,
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|
psram_cs_io: u8,
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|
psram_spiq_sd0_io: u8,
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|
psram_spid_sd1_io: u8,
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|
psram_spiwp_sd3_io: u8,
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|
psram_spihd_sd2_io: u8,
|
|
}
|
|
|
|
fn psram_gpio_config() {
|
|
unsafe extern "C" {
|
|
fn esp_rom_efuse_get_flash_gpio_info() -> u32;
|
|
|
|
/// Enable Quad I/O pin functions
|
|
///
|
|
/// Sets the HD & WP pin functions for Quad I/O modes, based on the
|
|
/// efuse SPI pin configuration.
|
|
///
|
|
/// [`wp_gpio_num`]: u8 Number of the WP pin to reconfigure for quad I/O
|
|
/// [`spiconfig`]: u32 Pin configuration, as returned from ets_efuse_get_spiconfig().
|
|
/// - If this parameter is 0, default SPI pins are used and wp_gpio_num parameter is
|
|
/// ignored.
|
|
/// - If this parameter is 1, default HSPI pins are used and wp_gpio_num parameter is
|
|
/// ignored.
|
|
/// - For other values, this parameter encodes the HD pin number and also the CLK pin
|
|
/// number. CLK pin selection is used to determine if HSPI or SPI peripheral will be
|
|
/// used (use HSPI if CLK pin is the HSPI clock pin, otherwise use SPI).
|
|
// Both HD & WP pins are configured via GPIO matrix to map to the selected peripheral.
|
|
fn esp_rom_spiflash_select_qio_pins(wp_gpio_num: u8, spiconfig: u32);
|
|
}
|
|
|
|
let psram_io = PsRamIo {
|
|
flash_clk_io: 30, // SPI_CLK_GPIO_NUM
|
|
flash_cs_io: 29, // SPI_CS0_GPIO_NUM
|
|
psram_clk_io: 30,
|
|
psram_cs_io: 26, // SPI_CS1_GPIO_NUM
|
|
psram_spiq_sd0_io: 31, // SPI_Q_GPIO_NUM
|
|
psram_spid_sd1_io: 32, // SPI_D_GPIO_NUM
|
|
psram_spiwp_sd3_io: 28, // SPI_WP_GPIO_NUM
|
|
psram_spihd_sd2_io: 27, // SPI_HD_GPIO_NUM
|
|
};
|
|
|
|
const ESP_ROM_EFUSE_FLASH_DEFAULT_SPI: u32 = 0;
|
|
|
|
unsafe {
|
|
let spiconfig = esp_rom_efuse_get_flash_gpio_info();
|
|
if spiconfig == ESP_ROM_EFUSE_FLASH_DEFAULT_SPI {
|
|
// FLASH pins(except wp / hd) are all configured via IO_MUX in
|
|
// rom.
|
|
} else {
|
|
// this case is currently not yet supported
|
|
panic!(
|
|
"Unsupported for now! The case 'FLASH pins are all configured via GPIO matrix in ROM.' is not yet supported."
|
|
);
|
|
|
|
// FLASH pins are all configured via GPIO matrix in ROM.
|
|
// psram_io.flash_clk_io =
|
|
// EFUSE_SPICONFIG_RET_SPICLK(spiconfig);
|
|
// psram_io.flash_cs_io = EFUSE_SPICONFIG_RET_SPICS0(spiconfig);
|
|
// psram_io.psram_spiq_sd0_io =
|
|
// EFUSE_SPICONFIG_RET_SPIQ(spiconfig);
|
|
// psram_io.psram_spid_sd1_io =
|
|
// EFUSE_SPICONFIG_RET_SPID(spiconfig);
|
|
// psram_io.psram_spihd_sd2_io =
|
|
// EFUSE_SPICONFIG_RET_SPIHD(spiconfig);
|
|
// psram_io.psram_spiwp_sd3_io =
|
|
// esp_rom_efuse_get_flash_wp_gpio();
|
|
}
|
|
esp_rom_spiflash_select_qio_pins(psram_io.psram_spiwp_sd3_io, spiconfig);
|
|
// s_psram_cs_io = psram_io.psram_cs_io;
|
|
}
|
|
}
|
|
|
|
const PSRAM_IO_MATRIX_DUMMY_20M: u32 = 0;
|
|
const PSRAM_IO_MATRIX_DUMMY_40M: u32 = 0;
|
|
const PSRAM_IO_MATRIX_DUMMY_80M: u32 = 0;
|
|
|
|
/// Register initialization for sram cache params and r/w commands
|
|
fn psram_cache_init(psram_cache_mode: PsramCacheSpeed, _vaddrmode: PsramVaddrMode) {
|
|
let mut extra_dummy = 0;
|
|
match psram_cache_mode {
|
|
PsramCacheSpeed::PsramCacheS80m => {
|
|
psram_clock_set(1);
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
|
|
}
|
|
PsramCacheSpeed::PsramCacheS40m => {
|
|
psram_clock_set(2);
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
}
|
|
PsramCacheSpeed::PsramCacheS26m => {
|
|
psram_clock_set(3);
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
|
|
}
|
|
PsramCacheSpeed::PsramCacheS20m => {
|
|
psram_clock_set(4);
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_20M;
|
|
}
|
|
_ => {
|
|
psram_clock_set(2);
|
|
}
|
|
}
|
|
|
|
const PSRAM_QUAD_WRITE: u32 = 0x38;
|
|
const PSRAM_FAST_READ_QUAD: u32 = 0xEB;
|
|
const PSRAM_FAST_READ_QUAD_DUMMY: u32 = 0x5;
|
|
|
|
unsafe {
|
|
let spi = SPI0::regs();
|
|
|
|
spi.cache_sctrl()
|
|
.modify(|_, w| w.usr_sram_dio().clear_bit()); // disable dio mode for cache command
|
|
|
|
spi.cache_sctrl().modify(|_, w| w.usr_sram_qio().set_bit()); // enable qio mode for cache command
|
|
|
|
spi.cache_sctrl()
|
|
.modify(|_, w| w.cache_sram_usr_rcmd().set_bit()); // enable cache read command
|
|
|
|
spi.cache_sctrl()
|
|
.modify(|_, w| w.cache_sram_usr_wcmd().set_bit()); // enable cache write command
|
|
|
|
// write address for cache command.
|
|
spi.cache_sctrl()
|
|
.modify(|_, w| w.sram_addr_bitlen().bits(23));
|
|
|
|
spi.cache_sctrl()
|
|
.modify(|_, w| w.usr_rd_sram_dummy().set_bit()); // enable cache read dummy
|
|
|
|
// config sram cache r/w command
|
|
spi.sram_dwr_cmd()
|
|
.modify(|_, w| w.cache_sram_usr_wr_cmd_bitlen().bits(7));
|
|
|
|
spi.sram_dwr_cmd().modify(|_, w| {
|
|
w.cache_sram_usr_wr_cmd_value()
|
|
.bits(PSRAM_QUAD_WRITE as u16)
|
|
});
|
|
|
|
spi.sram_drd_cmd()
|
|
.modify(|_, w| w.cache_sram_usr_rd_cmd_bitlen().bits(7));
|
|
|
|
spi.sram_drd_cmd().modify(|_, w| {
|
|
w.cache_sram_usr_rd_cmd_value()
|
|
.bits(PSRAM_FAST_READ_QUAD as u16)
|
|
});
|
|
|
|
// dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
|
spi.cache_sctrl().modify(|_, w| {
|
|
w.sram_rdummy_cyclelen()
|
|
.bits((PSRAM_FAST_READ_QUAD_DUMMY + extra_dummy) as u8)
|
|
});
|
|
|
|
// ESP-IDF has some code here to deal with `!CONFIG_FREERTOS_UNICORE` - not
|
|
// needed for ESP32-S2
|
|
|
|
// ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
|
|
spi.misc().modify(|_, w| w.cs1_dis().clear_bit());
|
|
}
|
|
}
|
|
|
|
fn psram_clock_set(freqdiv: i8) {
|
|
const SPI_MEM_SCLKCNT_N_S: u32 = 16;
|
|
const SPI_MEM_SCLKCNT_H_S: u32 = 8;
|
|
const SPI_MEM_SCLKCNT_L_S: u32 = 0;
|
|
|
|
if 1 >= freqdiv {
|
|
SPI0::regs()
|
|
.sram_clk()
|
|
.modify(|_, w| w.sclk_equ_sysclk().set_bit());
|
|
} else {
|
|
let freqbits: u32 = (((freqdiv - 1) as u32) << SPI_MEM_SCLKCNT_N_S)
|
|
| (((freqdiv / 2 - 1) as u32) << SPI_MEM_SCLKCNT_H_S)
|
|
| (((freqdiv - 1) as u32) << SPI_MEM_SCLKCNT_L_S);
|
|
unsafe {
|
|
SPI0::regs().sram_clk().modify(|_, w| w.bits(freqbits));
|
|
}
|
|
}
|
|
}
|
|
}
|