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69776eb638
* Abstract out LP-core targeting packages * Encode targets_lp_core in Cargo.toml * Encode architecture compatibility in Cargo.toml * Move semver_checked into Cargo.toml * Cache parsed tomls * Parse simple feature sets from Cargo.toml * Move all basic feature rules to Cargo.toml * Add check configs * Limit command length on Windows * Update cargo.rs * Add clippy configs * Use a single syntax, use a single doc-config line * Fix known problems * Run cargo check in CI command * Fix more problems * Fix esp-storage
44 lines
1.5 KiB
TOML
44 lines
1.5 KiB
TOML
[package]
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name = "esp-riscv-rt"
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version = "0.12.0"
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edition = "2024"
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rust-version = "1.88.0"
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description = "Minimal runtime / startup for RISC-V CPUs from Espressif"
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documentation = "https://docs.espressif.com/projects/rust/esp-riscv-rt/latest/"
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keywords = ["esp32", "espressif", "riscv", "runtime", "startup"]
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categories = ["embedded", "hardware-support", "no-std"]
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repository = "https://github.com/esp-rs/esp-hal"
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license = "MIT OR Apache-2.0"
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links = "esp-riscv-rt"
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[package.metadata.espressif]
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doc-config = { features = ["rtc-ram"] }
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requires_target = ["riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf"]
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check-configs = [
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{ features = [] },
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{ features = ["rtc-ram"] },
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{ features = ["no-mie-mip"] },
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{ features = ["rtc-ram", "no-mie-mip"] },
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]
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clippy-configs = [{ features = ["rtc-ram"] }]
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[lib]
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bench = false
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test = false
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[dependencies]
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document-features = "0.2.11"
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defmt = {version = "1.0.1", optional = true}
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riscv = "0.15.0"
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# We use the `single-hart` feature since starting up harts != 0 is handled by the HAL, not the runtime.
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riscv-rt = {version = "0.16.0", features = ["pre-init", "no-exceptions", "no-interrupts", "single-hart", "v-trap", "pre-default-start-trap"]}
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[features]
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## Indicate that the device does NOT support `mie` and `mip` CSRs.
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no-mie-mip = ["riscv-rt/no-xie-xip"]
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## Indicate that the device has RTC RAM.
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rtc-ram = []
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## Implement `defmt::Format`
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defmt = ["dep:defmt", "riscv-rt/defmt"]
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