6a663f8b1a
* Remove the chip-specific HAL packages * Update some doc comments which were missed, fix build script for ESP32/S2 * Refactor/update `esp-hal-procmacros` * Create the `examples` package, add back all of the previously existing examples * Use `xtask` automation package for checking examples and documentation in CI * Combine the `rt-riscv` and `rt-xtensa` features into a single `rt` feature * Bump MSRV to 1.76.0 (shocking!) * Re-document the features for the HAL * No need to re-export the `riscv` package like this * Make clippy happy, improve CI clippy checks * Update `CHANGELOG.md` * riscv: zero bss Co-authored-by: Björn Quentin <bjoernQ@users.noreply.github.com> * Address a number of review comments * Correct pin number in `hello_rgb` example for ESP32-C3 * Address the remaining review comments * More small tweaks/improvements * Fix RMT examples (#11) * Fix RMT examples * Remove logger-init * Make I2S examples work on ESP32 (#12) * Make I2S examples work on ESP32 * Remove logger init * Fix the direct-vectoring examples on all RISCV chips (#10) * Update GPIOs for some examples... * Embassy timer example fixes (#13) * Switch to generic queue instead of integrated for all examples * changelog * Update GPIO in another example, make `rustfmt` happy * Fix ESP32-S2 PSRAM * Avoid UART0 and SPI flash pins (#15) * Avoid UART0 and SPI flash pins * Fix spi_eh1_device_loopback for non-ESP32 * Update examples/src/bin/gpio_interrupt.rs Co-authored-by: Juraj Sadel <jurajsadel@gmail.com> --------- Co-authored-by: Juraj Sadel <jurajsadel@gmail.com> --------- Co-authored-by: Scott Mabin <scott@mabez.dev> Co-authored-by: Björn Quentin <bjoernQ@users.noreply.github.com> Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de> Co-authored-by: Juraj Sadel <jurajsadel@gmail.com>
esp-lp-hal
no_std HAL for the low-power RISC-V coprocessors found on the ESP32-C6, ESP32-S2, and ESP32-S3 from Espressif.
Implements a number of the traits defined in embedded-hal.
These devices uses the RISC-V ISA, which is officially supported by the Rust compiler via the riscv32imc-unknown-none-elf and riscv32imac-unknown-none-elf targets.
Please refer to the documentation for more information.
Documentation
Supported Devices
| Chip | Datasheet | Technical Reference Manual | Target |
|---|---|---|---|
| ESP32-C6 | ESP32-C6 | ESP32-C6 | riscv32imac-unknown-none-elf |
| ESP32-S2 | ESP32-S2 | ESP32-S2 | riscv32imc-unknown-none-elf |
| ESP32-S3 | ESP32-S3 | ESP32-S3 | riscv32imc-unknown-none-elf |
Resources
- The Rust Programming Language
- The Embedded Rust Book
- The Rust on ESP Book
- Datasheets:
- Technical Reference Manuals:
Getting Started
Installing the Rust Compiler Targets
The compilation targets for these devices are officially supported by the mainline Rust compiler and can be installed using rustup:
rustup target add riscv32imc-unknown-none-elf
rustup target add riscv32imac-unknown-none-elf
License
Licensed under either of:
- Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.