mirror of
https://github.com/esp-rs/esp-hal.git
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848029b152
* Mark interconnect as unstable * Explicitly set unstable feature in HIL tests * WIP append feature set name to artifact * Add name to feature sets, build all combinations * Fix tests * Provide a looping executor for stable async tests * Fix usb serial jtag * Hide interconnect types
52 lines
1.2 KiB
Rust
52 lines
1.2 KiB
Rust
//! Clock Monitor Test
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: unstable
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#![no_std]
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#![no_main]
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use esp_hal::rtc_cntl::Rtc;
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use hil_test as _;
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struct Context<'a> {
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rtc: Rtc<'a>,
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}
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#[cfg(test)]
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#[embedded_test::tests(default_timeout = 3)]
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mod tests {
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use super::*;
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#[init]
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fn init() -> Context<'static> {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let rtc = Rtc::new(peripherals.LPWR);
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Context { rtc }
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}
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#[test]
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fn test_estimated_clock(mut ctx: Context<'static>) {
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cfg_if::cfg_if! {
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if #[cfg(feature = "esp32c2")] {
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// 26 MHz
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let expected_range = 23..=29;
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} else if #[cfg(feature = "esp32h2")] {
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// 32 MHz
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let expected_range = 29..=35;
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} else {
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// 40 MHz
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let expected_range = 35..=45;
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}
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}
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let measured_frequency = ctx.rtc.estimate_xtal_frequency();
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defmt::assert!(
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expected_range.contains(&measured_frequency),
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"Measured frequency: {}",
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measured_frequency
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);
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}
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}
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