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* Create the `esp32c6-hal` package * Teach `esp-hal-common` about the ESP32-C6 * Get a number of peripheral drivers building for the ESP32-C6 bckup initial clocks_ii * Create the `esp32c6-hal` package C6: update * Simplify and fix the linker script update * C6: add I2S * Create the `esp32c6-hal` package * Teach `esp-hal-common` about the ESP32-C6 * Get a number of peripheral drivers building for the ESP32-C6 bckup initial clocks_ii * Create the `esp32c6-hal` package * C6: update * Simplify and fix the linker script * update * C6: add I2S * update * C6 Interrupts * C6: Update build.rs, linker scripts and initial examples * C6: RMT * Fix interrupt handling * Fix `ClockControl::configure` * C6: revert to I2S0 instead of just I2S * C6: rebase and update * RTC not buildable * Implement RWDT and SWD disable * C6: working LEDC * C6: working RMT * C6: add aes * C6: add mcpwm * C6: add rtc_cntln - not finished * C6: update and formatting * C6: add pcnt * C6: add examples and format * Remove inline assembly, fix interrupts and linker scripts * Remove unused features, update cargo config for atomic emu, misc cleanup * Get ADC building and example "working" (as much as it ever does) * Remove a bunch of unused constants which were copied from ESP-IDF * The `mcpwm` example now works correctly * Get `TWAI` peripheral driver building for C6 * Clean up the `rtc_cntl` module and get all the other HALs building again * Add the C6 to our CI workflow * Fix various things that have been missed when rebasing Still missing a few examples (`clock_monitor`, `embassy_spi`, `ram`) * C6: Small updates in wdt (#1) * C6: Update WDT * C6: Update examples with WDT update * Update `esp-println` dependency to fix build errors * Fix formatting issues causing pre-commit hook to fail * Get some more examples working * Working `ram` example * Sync with changes in `main` after rebasing * Working `embassy_spi` example * Use a git dependency for the PAC until we publish a release * Fix I2S for ESP32-C6 * Fix esp32c6 direct boot (#4) * Add direct boot support for C6 * Fix direct boot for c6 - Actually copy into rtc ram - remove dummy section that is no longer needed (was just a waste of flash space) - Move RTC stuff before the no load sections * Update RWDT and refactor RTC (#3) * C6: Update RWDT and add example, refactor RTC and add not-really-good example * Update based on review comments, resolve bunch of warnings and run cargo fmt * Update C6 esp-pacs rev commit * Fix clocks_ll/esp32c6.rs * Fix riscv interrupts * Remove clock_monitor example for now * RAM example works in direct-boot mode * Add a TODO for &mut TIMG0 and cargo fmt * Fix linker script after a bad rebase * Update CI and Cargo.toml embassy required features * use riscv32imac-unknown-none-elf target for C6 in CI * change default target to riscv32imac-unknown-none-elf * add riscv32imac-unknown-none-elf target to MSRV job * another cleanup --------- Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de> Co-authored-by: Jesse Braham <jesse@beta7.io> * Make required changes to include new `RADIO` peripheral * Use published versions of PAC and `esp-println` * Use the correct target extensions (`imac`) * Fix the super watchdog timer, plus a few more examples * Fix UART clock configuration * Make sure to sync UART registers when configuring AT cmd detection * Disable APM in direct-boot mode * Address a number of review comments * Fix `SPI` clocks and `rtc_watchdog` example (#6) * fix SPI clocks * run cargo fmt * Add comment about used default clk src * Fix rtc_watchdog example in BL mode * run cargo fmt * Update rtc_watchdog example that it works in DB mode * README and example fixes/cleanup * Add I2C peripheral enable and reset * Fix `ApbSarAdc` configuration in `system.rs` --------- Co-authored-by: bjoernQ <bjoern.quentin@mobile-j.de> Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com> Co-authored-by: Juraj Sadel <jurajsadel@gmail.com> Co-authored-by: Scott Mabin <scott@mabez.dev>
154 lines
4.7 KiB
Rust
154 lines
4.7 KiB
Rust
//! SPI loopback test
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//!
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//! Folowing pins are used:
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//! SCLK GPIO6
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//! MISO GPIO2
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//! MOSI GPIO7
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//! CS 1 GPIO3
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//! CS 2 GPIO4
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//! CS 3 GPIO5
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//!
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//! Depending on your target and the board you are using you have to change the
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//! pins.
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//!
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//! This example transfers data via SPI.
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//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
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//! data.
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#![no_std]
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#![no_main]
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use embedded_hal_1::spi::SpiDevice;
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use esp32c6_hal::{
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clock::ClockControl,
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gpio::IO,
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peripherals::Peripherals,
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prelude::*,
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spi::{Spi, SpiBusController, SpiMode},
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timer::TimerGroup,
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Delay,
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Rtc,
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};
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use esp_backtrace as _;
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use esp_println::{print, println};
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take();
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let mut system = peripherals.PCR.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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// Disable the watchdog timers. For the ESP32-C6, this includes the Super WDT,
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// the RTC WDT, and the TIMG WDTs.
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let mut rtc = Rtc::new(peripherals.LP_CLKRST);
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut wdt0 = timer_group0.wdt;
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let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
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let mut wdt1 = timer_group1.wdt;
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// Disable watchdog timers
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rtc.swd.disable();
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rtc.rwdt.disable();
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wdt0.disable();
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wdt1.disable();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let sclk = io.pins.gpio6;
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let miso = io.pins.gpio2;
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let mosi = io.pins.gpio7;
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let spi_controller = SpiBusController::from_spi(Spi::new_no_cs(
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peripherals.SPI2,
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sclk,
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mosi,
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miso,
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1000u32.kHz(),
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SpiMode::Mode0,
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&mut system.peripheral_clock_control,
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&clocks,
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));
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let mut spi_device_1 = spi_controller.add_device(io.pins.gpio3);
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let mut spi_device_2 = spi_controller.add_device(io.pins.gpio4);
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let mut spi_device_3 = spi_controller.add_device(io.pins.gpio5);
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let mut delay = Delay::new(&clocks);
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println!("=== SPI example with embedded-hal-1 traits ===");
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loop {
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// --- Symmetric transfer (Read as much as we write) ---
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print!("Starting symmetric transfer...");
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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spi_device_1.transfer(&mut read[..], &write[..]).unwrap();
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assert_eq!(write, read);
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spi_device_2.transfer(&mut read[..], &write[..]).unwrap();
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spi_device_3.transfer(&mut read[..], &write[..]).unwrap();
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Asymmetric transfer (Read more than we write) ---
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print!("Starting asymetric transfer (read > write)...");
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let mut read: [u8; 4] = [0x00; 4];
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spi_device_1
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.transfer(&mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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spi_device_2
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.transfer(&mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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spi_device_3
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.transfer(&mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Symmetric transfer with huge buffer ---
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// Only your RAM is the limit!
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print!("Starting huge transfer...");
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut read = [0x00u8; 4096];
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spi_device_1
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.transfer(&mut read[..], &write[..])
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.expect("Huge transfer failed");
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assert_eq!(write, read);
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spi_device_2
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.transfer(&mut read[..], &write[..])
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.expect("Huge transfer failed");
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spi_device_3
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.transfer(&mut read[..], &write[..])
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.expect("Huge transfer failed");
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Symmetric transfer with huge buffer in-place (No additional allocation
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// needed) ---
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print!("Starting huge transfer (in-place)...");
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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spi_device_1
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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spi_device_2
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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spi_device_3
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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}
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}
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