esp-hal/esp-lp-hal
Juraj Sadel 0b49b86f47
I2c and uart docs improvement (#3265)
* i2c: make blocking impl first in docs

* uart: group write and flush together

* reviews && use address instead of addr in lp i2c in pub API
2025-03-18 08:37:57 +00:00
..
2024-05-15 08:49:33 +00:00
2025-03-18 08:37:57 +00:00
2025-03-07 11:28:41 +00:00
2025-03-14 09:01:31 +00:00

esp-lp-hal

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Bare-metal (no_std) hardware abstraction layer for the low-power RISC-V coprocessors found in the ESP32-C6, ESP32-S2, and ESP32-S3 from Espressif.

Implements a number of blocking and, where applicable, async traits from the various packages in the embedded-hal repository.

For help getting started with this HAL, please refer to The Rust on ESP Book and the [documentation].

Documentation

Supported Devices

Chip Datasheet Technical Reference Manual Target
ESP32-C6 ESP32-C6 ESP32-C6 riscv32imac-unknown-none-elf
ESP32-S2 ESP32-S2 ESP32-S2 riscv32imc-unknown-none-elf
ESP32-S3 ESP32-S3 ESP32-S3 riscv32imc-unknown-none-elf

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile when using the latest stable Rust version at the time of the crate's release. It might compile with older versions, but that may change in any new release, including patches.

License

Licensed under either of:

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.