mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-29 21:30:39 +00:00
6db771c80e
Adds the `rt` feature which disables `esp_hal::init` and removes runtime symbols from the global name space. Disabling the `rt` feature is the recommended way to use esp-hal as a library.
940 lines
29 KiB
Rust
940 lines
29 KiB
Rust
//! Interrupt handling
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//!
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//! CPU interrupts 1 through 15 are reserved for each of the possible interrupt
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//! priorities.
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//!
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//! On chips with a PLIC CPU interrupts 1,2,5,6,9 .. 19 are used.
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//!
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//! ```rust, ignore
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//! interrupt1() => Priority::Priority1
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//! interrupt2() => Priority::Priority2
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//! ...
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//! interrupt15() => Priority::Priority15
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//! ```
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#[cfg(feature = "rt")]
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pub use esp_riscv_rt::TrapFrame;
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use procmacros::ram;
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use riscv::register::{mcause, mtvec};
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#[cfg(not(plic))]
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pub use self::classic::*;
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#[cfg(plic)]
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pub use self::plic::*;
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pub use self::vectored::*;
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use super::InterruptStatus;
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use crate::{
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pac,
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peripherals::{INTERRUPT_CORE0, Interrupt},
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system::Cpu,
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};
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/// Interrupt Error
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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/// The priority is not valid
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InvalidInterruptPriority,
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/// The CPU interrupt is a reserved interrupt
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CpuInterruptReserved,
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}
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/// Interrupt kind
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum InterruptKind {
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/// Level interrupt
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Level,
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/// Edge interrupt
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Edge,
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}
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/// Enumeration of available CPU interrupts.
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/// It is possible to create a handler for each of the interrupts. (e.g.
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/// `interrupt3`)
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#[repr(u32)]
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#[derive(Debug, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum CpuInterrupt {
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/// Interrupt number 1.
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Interrupt1 = 1,
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/// Interrupt number 2.
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Interrupt2,
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/// Interrupt number 3.
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Interrupt3,
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/// Interrupt number 4.
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Interrupt4,
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/// Interrupt number 5.
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Interrupt5,
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/// Interrupt number 6.
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Interrupt6,
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/// Interrupt number 7.
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Interrupt7,
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/// Interrupt number 8.
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Interrupt8,
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/// Interrupt number 9.
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Interrupt9,
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/// Interrupt number 10.
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Interrupt10,
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/// Interrupt number 11.
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Interrupt11,
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/// Interrupt number 12.
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Interrupt12,
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/// Interrupt number 13.
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Interrupt13,
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/// Interrupt number 14.
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Interrupt14,
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/// Interrupt number 15.
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Interrupt15,
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/// Interrupt number 16.
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Interrupt16,
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/// Interrupt number 17.
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Interrupt17,
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/// Interrupt number 18.
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Interrupt18,
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/// Interrupt number 19.
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Interrupt19,
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/// Interrupt number 20.
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Interrupt20,
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/// Interrupt number 21.
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Interrupt21,
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/// Interrupt number 22.
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Interrupt22,
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/// Interrupt number 23.
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Interrupt23,
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/// Interrupt number 24.
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Interrupt24,
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/// Interrupt number 25.
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Interrupt25,
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/// Interrupt number 26.
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Interrupt26,
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/// Interrupt number 27.
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Interrupt27,
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/// Interrupt number 28.
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Interrupt28,
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/// Interrupt number 29.
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Interrupt29,
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/// Interrupt number 30.
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Interrupt30,
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/// Interrupt number 31.
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Interrupt31,
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}
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/// Interrupt priority levels.
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#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, Hash)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[repr(u8)]
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pub enum Priority {
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/// No priority.
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None = 0,
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/// Priority level 1.
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Priority1,
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/// Priority level 2.
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Priority2,
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/// Priority level 3.
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Priority3,
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/// Priority level 4.
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Priority4,
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/// Priority level 5.
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Priority5,
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/// Priority level 6.
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Priority6,
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/// Priority level 7.
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Priority7,
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/// Priority level 8.
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Priority8,
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/// Priority level 9.
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Priority9,
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/// Priority level 10.
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Priority10,
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/// Priority level 11.
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Priority11,
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/// Priority level 12.
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Priority12,
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/// Priority level 13.
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Priority13,
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/// Priority level 14.
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Priority14,
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/// Priority level 15.
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Priority15,
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}
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impl Priority {
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/// Maximum interrupt priority
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pub const fn max() -> Priority {
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Priority::Priority15
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}
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/// Minimum interrupt priority
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pub const fn min() -> Priority {
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Priority::Priority1
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}
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}
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impl TryFrom<u32> for Priority {
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type Error = Error;
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fn try_from(value: u32) -> Result<Self, Self::Error> {
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match value {
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0 => Ok(Priority::None),
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1 => Ok(Priority::Priority1),
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2 => Ok(Priority::Priority2),
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3 => Ok(Priority::Priority3),
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4 => Ok(Priority::Priority4),
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5 => Ok(Priority::Priority5),
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6 => Ok(Priority::Priority6),
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7 => Ok(Priority::Priority7),
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8 => Ok(Priority::Priority8),
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9 => Ok(Priority::Priority9),
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10 => Ok(Priority::Priority10),
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11 => Ok(Priority::Priority11),
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12 => Ok(Priority::Priority12),
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13 => Ok(Priority::Priority13),
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14 => Ok(Priority::Priority14),
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15 => Ok(Priority::Priority15),
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_ => Err(Error::InvalidInterruptPriority),
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}
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}
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}
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impl TryFrom<u8> for Priority {
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type Error = Error;
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fn try_from(value: u8) -> Result<Self, Self::Error> {
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Priority::try_from(value as u32)
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}
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}
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/// The interrupts reserved by the HAL
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#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
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pub static RESERVED_INTERRUPTS: &[usize] = PRIORITY_TO_INTERRUPT;
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/// Enable an interrupt by directly binding it to a available CPU interrupt
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///
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/// Unless you are sure, you most likely want to use [`enable`] instead.
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///
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/// Trying using a reserved interrupt from [`RESERVED_INTERRUPTS`] will return
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/// an error.
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pub fn enable_direct(
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interrupt: Interrupt,
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level: Priority,
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cpu_interrupt: CpuInterrupt,
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) -> Result<(), Error> {
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if RESERVED_INTERRUPTS.contains(&(cpu_interrupt as _)) {
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return Err(Error::CpuInterruptReserved);
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}
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if matches!(level, Priority::None) {
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return Err(Error::InvalidInterruptPriority);
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}
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unsafe {
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map(Cpu::current(), interrupt, cpu_interrupt);
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set_priority(Cpu::current(), cpu_interrupt, level);
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enable_cpu_interrupt(cpu_interrupt);
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}
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Ok(())
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}
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/// Disable the given peripheral interrupt.
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pub fn disable(_core: Cpu, interrupt: Interrupt) {
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unsafe {
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let interrupt_number = interrupt as isize;
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let intr_map_base = crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32;
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// set to 0 to disable the peripheral interrupt on chips with an interrupt
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// controller other than PLIC use the disabled interrupt 31 otherwise
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intr_map_base
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.offset(interrupt_number)
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.write_volatile(DISABLED_CPU_INTERRUPT);
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}
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}
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/// Get status of peripheral interrupts
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#[inline]
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pub fn status(_core: Cpu) -> InterruptStatus {
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cfg_if::cfg_if! {
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if #[cfg(interrupts_status_registers = "3")] {
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InterruptStatus::from(
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INTERRUPT_CORE0::regs().intr_status_reg_0().read().bits(),
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INTERRUPT_CORE0::regs().intr_status_reg_1().read().bits(),
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INTERRUPT_CORE0::regs().int_status_reg_2().read().bits(),
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)
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} else if #[cfg(interrupts_status_registers = "4")] {
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InterruptStatus::from(
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INTERRUPT_CORE0::regs().intr_status_reg_0().read().bits(),
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INTERRUPT_CORE0::regs().intr_status_reg_1().read().bits(),
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INTERRUPT_CORE0::regs().intr_status_reg_2().read().bits(),
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INTERRUPT_CORE0::regs().intr_status_reg_3().read().bits(),
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)
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} else {
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InterruptStatus::from(
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INTERRUPT_CORE0::regs().intr_status_reg_0().read().bits(),
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INTERRUPT_CORE0::regs().intr_status_reg_1().read().bits(),
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)
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}
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}
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}
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/// Assign a peripheral interrupt to an CPU interrupt.
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///
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/// # Safety
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///
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/// Do not use CPU interrupts in the [`RESERVED_INTERRUPTS`].
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pub unsafe fn map(_core: Cpu, interrupt: Interrupt, which: CpuInterrupt) {
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let interrupt_number = interrupt as isize;
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let cpu_interrupt_number = which as isize;
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#[cfg(not(multi_core))]
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let intr_map_base = crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32;
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#[cfg(multi_core)]
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let intr_map_base = match _core {
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Cpu::ProCpu => crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32,
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Cpu::AppCpu => crate::soc::registers::INTERRUPT_MAP_BASE_APP_CPU as *mut u32,
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};
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unsafe {
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intr_map_base
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.offset(interrupt_number)
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.write_volatile(cpu_interrupt_number as u32 + EXTERNAL_INTERRUPT_OFFSET);
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}
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}
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/// Get cpu interrupt assigned to peripheral interrupt
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#[inline]
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unsafe fn assigned_cpu_interrupt(interrupt: Interrupt) -> Option<CpuInterrupt> {
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let interrupt_number = interrupt as isize;
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let intr_map_base = crate::soc::registers::INTERRUPT_MAP_BASE as *mut u32;
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let cpu_intr = unsafe { intr_map_base.offset(interrupt_number).read_volatile() };
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if cpu_intr > 0 && cpu_intr != DISABLED_CPU_INTERRUPT {
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Some(unsafe {
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core::mem::transmute::<u32, CpuInterrupt>(cpu_intr - EXTERNAL_INTERRUPT_OFFSET)
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})
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} else {
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None
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}
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}
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pub(crate) fn bound_cpu_interrupt_for(_cpu: Cpu, interrupt: Interrupt) -> Option<CpuInterrupt> {
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unsafe { assigned_cpu_interrupt(interrupt) }
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}
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mod vectored {
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use super::*;
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// Setup interrupts ready for vectoring
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#[doc(hidden)]
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pub(crate) unsafe fn init_vectoring() {
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for (prio, num) in PRIORITY_TO_INTERRUPT.iter().enumerate() {
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unsafe {
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set_kind(
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Cpu::current(),
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core::mem::transmute::<u32, CpuInterrupt>(*num as u32),
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InterruptKind::Level,
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);
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set_priority(
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Cpu::current(),
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core::mem::transmute::<u32, CpuInterrupt>(*num as u32),
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core::mem::transmute::<u8, Priority>((prio as u8) + 1),
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);
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enable_cpu_interrupt(core::mem::transmute::<u32, CpuInterrupt>(*num as u32));
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}
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}
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}
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/// Get the interrupts configured for the core at the given priority
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/// matching the given status
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#[inline]
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pub(crate) fn configured_interrupts(
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core: Cpu,
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status: InterruptStatus,
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priority: Priority,
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) -> InterruptStatus {
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unsafe {
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let mut res = InterruptStatus::empty();
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for interrupt_nr in status.iterator() {
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// safety: cast is safe because of repr(u16)
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if let Some(cpu_interrupt) =
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assigned_cpu_interrupt(core::mem::transmute::<u16, Interrupt>(
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interrupt_nr as u16,
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))
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&& priority_by_core(core, cpu_interrupt) == priority
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{
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res.set(interrupt_nr);
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}
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}
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res
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}
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}
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/// Enables a interrupt at a given priority
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///
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/// Note that interrupts still need to be enabled globally for interrupts
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/// to be serviced.
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pub fn enable(interrupt: Interrupt, level: Priority) -> Result<(), Error> {
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enable_on_cpu(Cpu::current(), interrupt, level)
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}
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pub(crate) fn enable_on_cpu(
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cpu: Cpu,
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interrupt: Interrupt,
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level: Priority,
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) -> Result<(), Error> {
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if matches!(level, Priority::None) {
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return Err(Error::InvalidInterruptPriority);
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}
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unsafe {
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let cpu_interrupt = core::mem::transmute::<u32, CpuInterrupt>(
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PRIORITY_TO_INTERRUPT[(level as usize) - 1] as u32,
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);
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map(cpu, interrupt, cpu_interrupt);
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enable_cpu_interrupt(cpu_interrupt);
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}
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Ok(())
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}
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/// Binds the given interrupt to the given handler.
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///
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/// # Safety
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///
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/// This will replace any previously bound interrupt handler
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pub unsafe fn bind_interrupt(interrupt: Interrupt, handler: unsafe extern "C" fn()) {
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unsafe {
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let ptr = &pac::__EXTERNAL_INTERRUPTS[interrupt as usize]._handler as *const _
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as *mut unsafe extern "C" fn();
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ptr.write_volatile(handler);
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}
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}
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/// Returns the currently bound interrupt handler.
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pub fn bound_handler(interrupt: Interrupt) -> Option<unsafe extern "C" fn()> {
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unsafe {
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let addr = pac::__EXTERNAL_INTERRUPTS[interrupt as usize]._handler;
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if addr as usize == 0 {
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return None;
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}
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Some(addr)
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}
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}
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}
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#[cfg(not(plic))]
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mod classic {
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use super::{CpuInterrupt, InterruptKind, Priority};
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use crate::{peripherals::INTERRUPT_CORE0, system::Cpu};
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#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
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pub(super) static DISABLED_CPU_INTERRUPT: u32 = 0;
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#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
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pub(super) static EXTERNAL_INTERRUPT_OFFSET: u32 = 0;
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#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
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pub(super) static PRIORITY_TO_INTERRUPT: &[usize] =
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&[1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];
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// First element is not used, just there to avoid a -1 in the interrupt handler.
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#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
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pub(super) static INTERRUPT_TO_PRIORITY: [u8; 16] =
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[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15];
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/// Enable a CPU interrupt
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///
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/// # Safety
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///
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/// Make sure there is an interrupt handler registered.
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pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
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let cpu_interrupt_number = which as isize;
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let intr = INTERRUPT_CORE0::regs();
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intr.cpu_int_enable()
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.modify(|r, w| unsafe { w.bits((1 << cpu_interrupt_number) | r.bits()) });
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}
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/// Set the interrupt kind (i.e. level or edge) of an CPU interrupt
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///
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/// The vectored interrupt handler will take care of clearing edge interrupt
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/// bits.
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pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
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unsafe {
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let intr = INTERRUPT_CORE0::regs();
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let cpu_interrupt_number = which as isize;
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let interrupt_type = match kind {
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InterruptKind::Level => 0,
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InterruptKind::Edge => 1,
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};
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intr.cpu_int_type().modify(|r, w| {
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w.bits(
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r.bits() & !(1 << cpu_interrupt_number)
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| (interrupt_type << cpu_interrupt_number),
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)
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});
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}
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}
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/// Set the priority level of an CPU interrupt
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///
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/// # Safety
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///
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/// Great care must be taken when using this function; avoid changing the
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/// priority of interrupts 1 - 15.
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pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
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let intr = INTERRUPT_CORE0::regs();
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intr.cpu_int_pri(which as usize)
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.write(|w| unsafe { w.map().bits(priority as u8) });
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}
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/// Clear a CPU interrupt
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#[inline]
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pub fn clear(_core: Cpu, which: CpuInterrupt) {
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unsafe {
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let cpu_interrupt_number = which as usize;
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let intr = INTERRUPT_CORE0::regs();
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intr.cpu_int_clear()
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.write(|w| w.bits(1 << cpu_interrupt_number));
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}
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}
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/// Get interrupt priority
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#[inline]
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pub(super) fn priority_by_core(_core: Cpu, cpu_interrupt: CpuInterrupt) -> Priority {
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priority(cpu_interrupt)
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}
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/// Get interrupt priority - called by assembly code
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#[inline]
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pub(super) fn priority(cpu_interrupt: CpuInterrupt) -> Priority {
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let intr = INTERRUPT_CORE0::regs();
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unsafe {
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core::mem::transmute::<u8, Priority>(
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intr.cpu_int_pri(cpu_interrupt as usize).read().map().bits(),
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)
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}
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}
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/// Get the current run level (the level below which interrupts are masked).
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pub fn current_runlevel() -> Priority {
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let intr = INTERRUPT_CORE0::regs();
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let prev_interrupt_priority = intr.cpu_int_thresh().read().bits().saturating_sub(1) as u8;
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unwrap!(Priority::try_from(prev_interrupt_priority))
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}
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/// Changes the current run level (the level below which interrupts are
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/// masked), and returns the previous run level.
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///
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/// # Safety
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///
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/// This function must only be used to raise the runlevel and to restore it
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|
/// to a previous value. It must not be used to arbitrarily lower the
|
|
/// runlevel.
|
|
pub(crate) unsafe fn change_current_runlevel(level: Priority) -> Priority {
|
|
let prev_interrupt_priority = current_runlevel();
|
|
|
|
// The CPU responds to interrupts `>= level`, but we want to also disable
|
|
// interrupts at `level` so we set the threshold to `level + 1`.
|
|
INTERRUPT_CORE0::regs()
|
|
.cpu_int_thresh()
|
|
.write(|w| unsafe { w.bits(level as u32 + 1) });
|
|
|
|
prev_interrupt_priority
|
|
}
|
|
|
|
#[cfg(feature = "rt")]
|
|
mod rt {
|
|
use super::*;
|
|
|
|
#[unsafe(link_section = ".trap")]
|
|
#[unsafe(no_mangle)]
|
|
pub(super) unsafe extern "C" fn _handle_priority() -> u32 {
|
|
// Both C6 and H2 have 5 bits of code. The riscv crate masks 31 bits, which then
|
|
// causes a bounds check to be present.
|
|
let interrupt_id: usize = riscv::register::mcause::read().bits() & 0x1f;
|
|
let intr = INTERRUPT_CORE0::regs();
|
|
let interrupt_priority = unsafe {
|
|
intr.cpu_int_pri(0)
|
|
.as_ptr()
|
|
.add(interrupt_id)
|
|
.read_volatile()
|
|
};
|
|
|
|
let prev_interrupt_priority = intr.cpu_int_thresh().read().bits();
|
|
if interrupt_priority < 15 {
|
|
// leave interrupts disabled if interrupt is of max priority.
|
|
intr.cpu_int_thresh()
|
|
.write(|w| unsafe { w.bits(interrupt_priority + 1) }); // set the prio threshold to 1 more than current interrupt prio
|
|
unsafe { riscv::interrupt::enable() };
|
|
}
|
|
prev_interrupt_priority
|
|
}
|
|
|
|
#[unsafe(link_section = ".trap")]
|
|
#[unsafe(no_mangle)]
|
|
unsafe extern "C" fn _restore_priority(stored_prio: u32) {
|
|
riscv::interrupt::disable();
|
|
let intr = INTERRUPT_CORE0::regs();
|
|
intr.cpu_int_thresh()
|
|
.write(|w| unsafe { w.bits(stored_prio) });
|
|
}
|
|
|
|
/// Globally exported so assembly code can call it.
|
|
#[unsafe(no_mangle)]
|
|
unsafe extern "C" fn priority(cpu_interrupt: CpuInterrupt) -> Priority {
|
|
super::priority(cpu_interrupt)
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(plic)]
|
|
mod plic {
|
|
use super::{CpuInterrupt, InterruptKind, Priority};
|
|
use crate::{peripherals::PLIC_MX, system::Cpu};
|
|
|
|
#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
|
|
pub(super) static DISABLED_CPU_INTERRUPT: u32 = 31;
|
|
|
|
#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
|
|
pub(super) static EXTERNAL_INTERRUPT_OFFSET: u32 = 0;
|
|
|
|
// don't use interrupts reserved for CLIC (0,3,4,7)
|
|
// for some reason also CPU interrupt 8 doesn't work by default since it's
|
|
// disabled after reset - so don't use that, too
|
|
#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
|
|
pub(super) static PRIORITY_TO_INTERRUPT: &[usize] =
|
|
&[1, 2, 5, 6, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19];
|
|
|
|
// First element is not used, just there to avoid a -1 in the interrupt handler.
|
|
#[cfg_attr(place_switch_tables_in_ram, unsafe(link_section = ".rwtext"))]
|
|
pub(super) static INTERRUPT_TO_PRIORITY: [u8; 20] = [
|
|
0, 1, 2, 0, 0, 3, 4, 0, 0, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
|
|
];
|
|
|
|
/// Enable a CPU interrupt
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// Make sure there is an interrupt handler registered.
|
|
pub unsafe fn enable_cpu_interrupt(which: CpuInterrupt) {
|
|
unsafe {
|
|
PLIC_MX::regs().mxint_enable().modify(|r, w| {
|
|
let old = r.cpu_mxint_enable().bits();
|
|
let new = old | (1 << (which as isize));
|
|
w.cpu_mxint_enable().bits(new)
|
|
});
|
|
}
|
|
}
|
|
|
|
/// Set the interrupt kind (i.e. level or edge) of an CPU interrupt
|
|
///
|
|
/// The vectored interrupt handler will take care of clearing edge interrupt
|
|
/// bits.
|
|
pub fn set_kind(_core: Cpu, which: CpuInterrupt, kind: InterruptKind) {
|
|
let interrupt_type = match kind {
|
|
InterruptKind::Level => 0,
|
|
InterruptKind::Edge => 1,
|
|
};
|
|
|
|
unsafe {
|
|
PLIC_MX::regs().mxint_type().modify(|r, w| {
|
|
let old = r.cpu_mxint_type().bits();
|
|
let new = old & !(1 << (which as isize)) | (interrupt_type << (which as isize));
|
|
w.cpu_mxint_type().bits(new)
|
|
});
|
|
}
|
|
}
|
|
|
|
/// Set the priority level of an CPU interrupt
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// Great care must be taken when using this function; avoid changing the
|
|
/// priority of interrupts 1 - 15.
|
|
pub unsafe fn set_priority(_core: Cpu, which: CpuInterrupt, priority: Priority) {
|
|
unsafe {
|
|
PLIC_MX::regs()
|
|
.mxint_pri(which as usize)
|
|
.modify(|_, w| w.cpu_mxint_pri().bits(priority as u8));
|
|
}
|
|
}
|
|
|
|
/// Clear a CPU interrupt
|
|
#[inline]
|
|
pub fn clear(_core: Cpu, which: CpuInterrupt) {
|
|
unsafe {
|
|
PLIC_MX::regs().mxint_clear().modify(|r, w| {
|
|
let old = r.cpu_mxint_clear().bits();
|
|
let new = old | (1 << (which as isize));
|
|
w.cpu_mxint_clear().bits(new)
|
|
});
|
|
}
|
|
}
|
|
|
|
/// Get interrupt priority for the CPU
|
|
#[inline]
|
|
pub fn priority_by_core(_core: Cpu, cpu_interrupt: CpuInterrupt) -> Priority {
|
|
priority(cpu_interrupt)
|
|
}
|
|
|
|
#[inline]
|
|
/// Get interrupt priority.
|
|
pub fn priority(cpu_interrupt: CpuInterrupt) -> Priority {
|
|
let prio = PLIC_MX::regs()
|
|
.mxint_pri(cpu_interrupt as usize)
|
|
.read()
|
|
.cpu_mxint_pri()
|
|
.bits();
|
|
unsafe { core::mem::transmute::<u8, Priority>(prio) }
|
|
}
|
|
|
|
/// Get the current run level (the level below which interrupts are masked).
|
|
pub fn current_runlevel() -> Priority {
|
|
let prev_interrupt_priority = PLIC_MX::regs()
|
|
.mxint_thresh()
|
|
.read()
|
|
.cpu_mxint_thresh()
|
|
.bits()
|
|
.saturating_sub(1);
|
|
|
|
unwrap!(Priority::try_from(prev_interrupt_priority))
|
|
}
|
|
|
|
/// Changes the current run level (the level below which interrupts are
|
|
/// masked), and returns the previous run level.
|
|
///
|
|
/// # Safety
|
|
///
|
|
/// This function must only be used to raise the runlevel and to restore it
|
|
/// to a previous value. It must not be used to arbitrarily lower the
|
|
/// runlevel.
|
|
pub(crate) unsafe fn change_current_runlevel(level: Priority) -> Priority {
|
|
let prev_interrupt_priority = current_runlevel();
|
|
|
|
// The CPU responds to interrupts `>= level`, but we want to also disable
|
|
// interrupts at `level` so we set the threshold to `level + 1`.
|
|
PLIC_MX::regs()
|
|
.mxint_thresh()
|
|
.write(|w| unsafe { w.cpu_mxint_thresh().bits(level as u8 + 1) });
|
|
|
|
prev_interrupt_priority
|
|
}
|
|
|
|
#[cfg(feature = "rt")]
|
|
mod rt {
|
|
use super::*;
|
|
/// Get interrupt priority - called by assembly code
|
|
#[unsafe(no_mangle)]
|
|
pub(super) unsafe extern "C" fn priority(cpu_interrupt: CpuInterrupt) -> Priority {
|
|
super::priority(cpu_interrupt)
|
|
}
|
|
|
|
#[unsafe(no_mangle)]
|
|
#[unsafe(link_section = ".trap")]
|
|
pub(super) unsafe extern "C" fn _handle_priority() -> u32 {
|
|
let interrupt_id: usize = riscv::register::mcause::read().code(); // MSB is whether its exception or interrupt.
|
|
let interrupt_priority = PLIC_MX::regs()
|
|
.mxint_pri(interrupt_id)
|
|
.read()
|
|
.cpu_mxint_pri()
|
|
.bits();
|
|
|
|
let prev_interrupt_priority = PLIC_MX::regs()
|
|
.mxint_thresh()
|
|
.read()
|
|
.cpu_mxint_thresh()
|
|
.bits();
|
|
if interrupt_priority < 15 {
|
|
// leave interrupts disabled if interrupt is of max priority.
|
|
PLIC_MX::regs()
|
|
.mxint_thresh()
|
|
.write(|w| unsafe { w.cpu_mxint_thresh().bits(interrupt_priority + 1) });
|
|
|
|
unsafe {
|
|
riscv::interrupt::enable();
|
|
}
|
|
}
|
|
prev_interrupt_priority as u32
|
|
}
|
|
|
|
#[unsafe(no_mangle)]
|
|
#[unsafe(link_section = ".trap")]
|
|
pub(super) unsafe extern "C" fn _restore_priority(stored_prio: u32) {
|
|
riscv::interrupt::disable();
|
|
PLIC_MX::regs()
|
|
.mxint_thresh()
|
|
.write(|w| unsafe { w.cpu_mxint_thresh().bits(stored_prio as u8) });
|
|
}
|
|
}
|
|
}
|
|
|
|
#[cfg(feature = "rt")]
|
|
mod rt {
|
|
use esp_riscv_rt::TrapFrame;
|
|
|
|
use super::*;
|
|
|
|
/// # Safety
|
|
///
|
|
/// This function is called from an assembly trap handler.
|
|
#[doc(hidden)]
|
|
#[unsafe(link_section = ".trap.rust")]
|
|
#[unsafe(export_name = "_start_trap_rust_hal")]
|
|
unsafe extern "C" fn start_trap_rust_hal(trap_frame: *mut TrapFrame) {
|
|
assert!(
|
|
mcause::read().is_exception(),
|
|
"Arrived into _start_trap_rust_hal but mcause is not an exception!"
|
|
);
|
|
unsafe extern "C" {
|
|
fn ExceptionHandler(tf: *mut TrapFrame);
|
|
}
|
|
unsafe {
|
|
ExceptionHandler(trap_frame);
|
|
}
|
|
}
|
|
|
|
#[doc(hidden)]
|
|
#[unsafe(no_mangle)]
|
|
unsafe fn _setup_interrupts() {
|
|
unsafe extern "C" {
|
|
static _vector_table: *const u32;
|
|
}
|
|
|
|
unsafe {
|
|
// disable all known interrupts
|
|
// at least after the 2nd stage bootloader there are some interrupts enabled
|
|
// (e.g. UART)
|
|
for peripheral_interrupt in 0..255 {
|
|
crate::peripherals::Interrupt::try_from(peripheral_interrupt)
|
|
.map(|intr| {
|
|
#[cfg(multi_core)]
|
|
disable(Cpu::AppCpu, intr);
|
|
disable(Cpu::ProCpu, intr);
|
|
})
|
|
.ok();
|
|
}
|
|
|
|
let vec_table = &_vector_table as *const _ as usize;
|
|
mtvec::write(vec_table, mtvec::TrapMode::Vectored);
|
|
|
|
crate::interrupt::init_vectoring();
|
|
};
|
|
|
|
#[cfg(plic)]
|
|
unsafe {
|
|
core::arch::asm!("csrw mie, {0}", in(reg) u32::MAX);
|
|
}
|
|
}
|
|
|
|
#[unsafe(no_mangle)]
|
|
#[ram]
|
|
unsafe fn handle_interrupts(cpu_intr: CpuInterrupt, context: &mut TrapFrame) {
|
|
let core = Cpu::current();
|
|
let status = status(core);
|
|
|
|
// this has no effect on level interrupts, but the interrupt may be an edge one
|
|
// so we clear it anyway
|
|
clear(core, cpu_intr);
|
|
|
|
let priority = INTERRUPT_TO_PRIORITY[cpu_intr as usize];
|
|
let prio: Priority = unsafe { core::mem::transmute(priority) };
|
|
let configured_interrupts = vectored::configured_interrupts(core, status, prio);
|
|
|
|
for interrupt_nr in configured_interrupts.iterator() {
|
|
// Don't use `Interrupt::try_from`. It's slower and placed in flash
|
|
let interrupt: Interrupt = unsafe { core::mem::transmute(interrupt_nr as u16) };
|
|
unsafe {
|
|
handle_interrupt(interrupt, context);
|
|
}
|
|
}
|
|
}
|
|
|
|
#[inline(always)]
|
|
unsafe fn handle_interrupt(interrupt: Interrupt, save_frame: &mut TrapFrame) {
|
|
unsafe extern "C" {
|
|
// defined in each hal
|
|
fn EspDefaultHandler(interrupt: Interrupt);
|
|
}
|
|
|
|
let handler = unsafe { pac::__EXTERNAL_INTERRUPTS[interrupt as usize]._handler };
|
|
|
|
if core::ptr::eq(
|
|
handler as *const _,
|
|
EspDefaultHandler as *const unsafe extern "C" fn(),
|
|
) {
|
|
unsafe { EspDefaultHandler(interrupt) };
|
|
} else {
|
|
let handler: fn(&mut TrapFrame) = unsafe {
|
|
core::mem::transmute::<unsafe extern "C" fn(), fn(&mut TrapFrame)>(handler)
|
|
};
|
|
handler(save_frame);
|
|
}
|
|
}
|
|
|
|
// The compiler generates quite unfortunate code for
|
|
// ```rust,ignore
|
|
// #[no_mangle]
|
|
// #[ram]
|
|
// unsafe fn interrupt1(context: &mut TrapFrame) {
|
|
// handle_interrupts(CpuInterrupt::Interrupt1, context)
|
|
// }
|
|
// ```
|
|
//
|
|
// Resulting in
|
|
// ```asm,ignore
|
|
// interrupt1:
|
|
// add sp,sp,-16
|
|
// sw ra,12(sp)
|
|
// sw s0,8(sp)
|
|
// add s0,sp,16
|
|
// mv a1,a0
|
|
// li a0,1
|
|
// lw ra,12(sp)
|
|
// lw s0,8(sp)
|
|
// add sp,sp,16
|
|
// auipc t1,0x0
|
|
// jr handle_interrupts
|
|
// ```
|
|
//
|
|
// We can do better manually - use Rust again once/if that changes
|
|
macro_rules! interrupt_handler {
|
|
($num:literal) => {
|
|
core::arch::global_asm! {
|
|
concat!(
|
|
r#"
|
|
.section .rwtext, "ax"
|
|
.global interrupt"#,$num,r#"
|
|
|
|
interrupt"#,$num,r#":
|
|
mv a1, a0
|
|
li a0,"#,$num,r#"
|
|
j handle_interrupts
|
|
"#
|
|
)
|
|
}
|
|
};
|
|
}
|
|
|
|
interrupt_handler!(1);
|
|
interrupt_handler!(2);
|
|
interrupt_handler!(3);
|
|
interrupt_handler!(4);
|
|
interrupt_handler!(5);
|
|
interrupt_handler!(6);
|
|
interrupt_handler!(7);
|
|
interrupt_handler!(8);
|
|
interrupt_handler!(9);
|
|
interrupt_handler!(10);
|
|
interrupt_handler!(11);
|
|
interrupt_handler!(12);
|
|
interrupt_handler!(13);
|
|
interrupt_handler!(14);
|
|
interrupt_handler!(15);
|
|
|
|
#[cfg(plic)]
|
|
interrupt_handler!(16);
|
|
#[cfg(plic)]
|
|
interrupt_handler!(17);
|
|
#[cfg(plic)]
|
|
interrupt_handler!(18);
|
|
#[cfg(plic)]
|
|
interrupt_handler!(19);
|
|
}
|