mirror of
https://github.com/esp-rs/esp-hal.git
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9064177e99
* wip: timg embassy driver - read_raw on timg renamed to now() - timg initialized and stored in static for use in the embassy driver - timg sets alarm value - untested whether alarms actually trigger * TIMG timer driver for esp32, esp32s3 - Adds the timg timer block as a time driver for embassy - Not enabled on the C3 as it only has one timer block, better to use systimer - s2 example added but can't build due to atomic requirements in futures-core * Add S2 atomic support with emulation, fixup embassy support for the S2 * Move executor & static-cell to dev deps. Make eha optional * Add c2 support, run fmt * Update to crates.io embassy releases * Update eha * update timg time driver to new trait * Remove exception feature of esp-backtrace and use the user handler for backtracing * Add async testing workflow * Update systick example * Fix S2 examples * Update xtensa-toolchain * set rustflags for s2 target * Disable systick for esp32s2 until we can fix the noted issues * review improvements - Fix intr prio array being off by one - emabssy time prio interrupt set to max prio - use cfg instead of feature for systick detection * Update example time delays
93 lines
2.5 KiB
Rust
93 lines
2.5 KiB
Rust
//! This demos basic usage of RMT / PulseControl
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//! Use a logic analyzer to see the generated pulses.
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//! The correct output is only achieved when running in release mode.
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#![no_std]
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#![no_main]
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use esp32s2_hal::{
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clock::ClockControl,
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gpio::IO,
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pac::Peripherals,
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prelude::*,
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pulse_control::{ConfiguredChannel, OutputChannel, PulseCode, RepeatMode},
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timer::TimerGroup,
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PulseControl,
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Rtc,
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};
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use esp_backtrace as _;
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use xtensa_atomic_emulation_trap as _;
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use xtensa_lx_rt::entry;
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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let mut system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut wdt = timer_group0.wdt;
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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// Disable MWDT and RWDT (Watchdog) flash boot protection
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wdt.disable();
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rtc.rwdt.disable();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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// Configure RMT peripheral globally
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let pulse = PulseControl::new(peripherals.RMT, &mut system.peripheral_clock_control).unwrap();
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let mut rmt_channel0 = pulse.channel0;
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// Set up channel
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rmt_channel0
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.set_idle_output_level(false)
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.set_carrier_modulation(false)
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.set_channel_divider(1)
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.set_idle_output(true);
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// Assign GPIO pin where pulses should be sent to
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let mut rmt_channel0 = rmt_channel0.assign_pin(io.pins.gpio4);
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// Create pulse sequence
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let mut seq = [PulseCode {
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level1: true,
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length1: 0u32.nanos(),
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level2: false,
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length2: 0u32.nanos(),
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}; 128];
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// -1 to make sure that the last element is a transmission end marker (i.e.
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// lenght 0)
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for i in 0..(seq.len() - 1) {
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seq[i] = PulseCode {
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level1: true,
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length1: (10u32 * (i as u32 + 1u32)).nanos(),
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level2: false,
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length2: 60u32.nanos(),
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};
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}
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loop {
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// Send sequence
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rmt_channel0
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.send_pulse_sequence(RepeatMode::SingleShot, &seq)
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.unwrap();
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}
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}
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#[xtensa_lx_rt::exception]
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fn exception(cause: xtensa_lx_rt::exception::ExceptionCause, frame: xtensa_lx_rt::exception::Context) {
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use esp_println::*;
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println!("\n\nException occured {:?} {:x?}", cause, frame);
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let backtrace = esp_backtrace::arch::backtrace();
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for b in backtrace.iter() {
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if let Some(addr) = b {
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println!("0x{:x}", addr)
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}
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}
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}
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