mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-02 14:44:42 +00:00
9064177e99
* wip: timg embassy driver - read_raw on timg renamed to now() - timg initialized and stored in static for use in the embassy driver - timg sets alarm value - untested whether alarms actually trigger * TIMG timer driver for esp32, esp32s3 - Adds the timg timer block as a time driver for embassy - Not enabled on the C3 as it only has one timer block, better to use systimer - s2 example added but can't build due to atomic requirements in futures-core * Add S2 atomic support with emulation, fixup embassy support for the S2 * Move executor & static-cell to dev deps. Make eha optional * Add c2 support, run fmt * Update to crates.io embassy releases * Update eha * update timg time driver to new trait * Remove exception feature of esp-backtrace and use the user handler for backtracing * Add async testing workflow * Update systick example * Fix S2 examples * Update xtensa-toolchain * set rustflags for s2 target * Disable systick for esp32s2 until we can fix the noted issues * review improvements - Fix intr prio array being off by one - emabssy time prio interrupt set to max prio - use cfg instead of feature for systick detection * Update example time delays
109 lines
3.1 KiB
Rust
109 lines
3.1 KiB
Rust
//! This shows some of the interrupts that can be generated by UART/Serial.
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//! Use a proper serial terminal to connect to the board (espmonitor and
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//! espflash won't work)
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#![no_std]
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#![no_main]
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use core::{cell::RefCell, fmt::Write};
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use critical_section::Mutex;
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use esp32s2_hal::{
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clock::ClockControl,
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interrupt,
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pac::{self, Peripherals, UART0},
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prelude::*,
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serial::config::AtCmdConfig,
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timer::TimerGroup,
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Rtc,
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Serial,
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};
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use esp_backtrace as _;
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use xtensa_atomic_emulation_trap as _;
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use nb::block;
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use xtensa_lx_rt::entry;
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static SERIAL: Mutex<RefCell<Option<Serial<UART0>>>> = Mutex::new(RefCell::new(None));
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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// Disable the TIMG watchdog timer.
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut timer0 = timer_group0.timer0;
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let mut wdt0 = timer_group0.wdt;
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let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
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let mut wdt1 = timer_group1.wdt;
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let mut serial0 = Serial::new(peripherals.UART0);
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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// Disable MWDT and RWDT (Watchdog) flash boot protection
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wdt0.disable();
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wdt1.disable();
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rtc.rwdt.disable();
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serial0.set_at_cmd(AtCmdConfig::new(None, None, None, b'#', None));
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serial0.set_rx_fifo_full_threshold(30);
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serial0.listen_at_cmd();
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serial0.listen_rx_fifo_full();
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interrupt::enable(pac::Interrupt::UART0, interrupt::Priority::Priority2).unwrap();
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timer0.start(1u64.secs());
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critical_section::with(|cs| SERIAL.borrow_ref_mut(cs).replace(serial0));
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loop {
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critical_section::with(|cs| {
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let mut serial = SERIAL.borrow_ref_mut(cs);
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let serial = serial.as_mut().unwrap();
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writeln!(serial, "Hello World! Send a single `#` character or send at least 30 characters and see the interrupts trigger.").ok();
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});
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block!(timer0.wait()).unwrap();
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}
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}
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#[interrupt]
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fn UART0() {
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critical_section::with(|cs| {
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let mut serial = SERIAL.borrow_ref_mut(cs);
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let serial = serial.as_mut().unwrap();
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let mut cnt = 0;
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while let nb::Result::Ok(_c) = serial.read() {
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cnt += 1;
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}
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writeln!(serial, "Read {} bytes", cnt,).ok();
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writeln!(
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serial,
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"Interrupt AT-CMD: {} RX-FIFO-FULL: {}",
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serial.at_cmd_interrupt_set(),
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serial.rx_fifo_full_interrupt_set(),
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)
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.ok();
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serial.reset_at_cmd_interrupt();
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serial.reset_rx_fifo_full_interrupt();
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});
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}
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#[xtensa_lx_rt::exception]
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fn exception(cause: xtensa_lx_rt::exception::ExceptionCause, frame: xtensa_lx_rt::exception::Context) {
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use esp_println::*;
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println!("\n\nException occured {:?} {:x?}", cause, frame);
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let backtrace = esp_backtrace::arch::backtrace();
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for b in backtrace.iter() {
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if let Some(addr) = b {
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println!("0x{:x}", addr)
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}
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}
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} |