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https://github.com/esp-rs/esp-hal.git
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* Update the `GDMA` driver to support the ESP32-H2 * Update the `SPI` driver to support the ESP32-H2 * Add `SPI` examples for ESP32-H2 * Update CHANGELOG * Remove copy-pasted references to ESP32-C6 * Update GPIO pins used in SPI examples, add `qspi_flash` example * Update SPI clock configuration to produce correct clock rate * Correct comment regarding clock source frequency Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com> * H2: Add PLL_48M_CLK src to ClockControl and RawClocks * H2: Use PLL_48M_CLK as SPI clk src * H2: cleanup commented block in SPI driver * H2: update docs comment in embassy_spi example * fmt * Add a new line in embassy_spi example --------- Co-authored-by: Sergio Gasquez Arcos <sergio.gasquez@gmail.com> Co-authored-by: Juraj Sadel <juraj.sadel@espressif.com>
162 lines
4.9 KiB
Rust
162 lines
4.9 KiB
Rust
//! SPI loopback test
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//!
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//! Folowing pins are used:
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//! SCLK GPIO1
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//! MISO GPIO2
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//! MOSI GPIO3
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//! CS 1 GPIO11
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//! CS 2 GPIO12
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//! CS 3 GPIO25
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//!
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//! Depending on your target and the board you are using you have to change the
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//! pins.
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//!
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//! This example transfers data via SPI.
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//! Connect MISO and MOSI pins to see the outgoing data is read as incoming
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//! data.
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#![no_std]
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#![no_main]
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use embedded_hal_1::spi::SpiDevice;
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use esp32h2_hal::{
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clock::ClockControl,
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gpio::IO,
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peripherals::Peripherals,
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prelude::*,
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spi::{Spi, SpiBusController, SpiMode},
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timer::TimerGroup,
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Delay,
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Rtc,
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};
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use esp_backtrace as _;
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use esp_println::{print, println};
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take();
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let mut system = peripherals.PCR.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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// Disable the watchdog timers. For the ESP32-H2, this includes the Super WDT,
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// the RTC WDT, and the TIMG WDTs.
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let mut rtc = Rtc::new(peripherals.LP_CLKRST);
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let timer_group0 = TimerGroup::new(
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peripherals.TIMG0,
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&clocks,
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&mut system.peripheral_clock_control,
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);
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let mut wdt0 = timer_group0.wdt;
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let timer_group1 = TimerGroup::new(
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peripherals.TIMG1,
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&clocks,
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&mut system.peripheral_clock_control,
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);
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let mut wdt1 = timer_group1.wdt;
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// Disable watchdog timers
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rtc.swd.disable();
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rtc.rwdt.disable();
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wdt0.disable();
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wdt1.disable();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let sclk = io.pins.gpio1;
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let miso = io.pins.gpio2;
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let mosi = io.pins.gpio3;
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let spi_controller = SpiBusController::from_spi(Spi::new_no_cs(
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peripherals.SPI2,
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sclk,
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mosi,
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miso,
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1000u32.kHz(),
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SpiMode::Mode0,
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&mut system.peripheral_clock_control,
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&clocks,
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));
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let mut spi_device_1 = spi_controller.add_device(io.pins.gpio11);
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let mut spi_device_2 = spi_controller.add_device(io.pins.gpio12);
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let mut spi_device_3 = spi_controller.add_device(io.pins.gpio25);
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let mut delay = Delay::new(&clocks);
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println!("=== SPI example with embedded-hal-1 traits ===");
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loop {
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// --- Symmetric transfer (Read as much as we write) ---
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print!("Starting symmetric transfer...");
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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spi_device_1.transfer(&mut read[..], &write[..]).unwrap();
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assert_eq!(write, read);
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spi_device_2.transfer(&mut read[..], &write[..]).unwrap();
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spi_device_3.transfer(&mut read[..], &write[..]).unwrap();
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Asymmetric transfer (Read more than we write) ---
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print!("Starting asymetric transfer (read > write)...");
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let mut read: [u8; 4] = [0x00; 4];
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spi_device_1
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.transfer(&mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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spi_device_2
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.transfer(&mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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spi_device_3
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.transfer(&mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Symmetric transfer with huge buffer ---
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// Only your RAM is the limit!
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print!("Starting huge transfer...");
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut read = [0x00u8; 4096];
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spi_device_1
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.transfer(&mut read[..], &write[..])
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.expect("Huge transfer failed");
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assert_eq!(write, read);
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spi_device_2
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.transfer(&mut read[..], &write[..])
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.expect("Huge transfer failed");
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spi_device_3
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.transfer(&mut read[..], &write[..])
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.expect("Huge transfer failed");
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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// --- Symmetric transfer with huge buffer in-place (No additional allocation
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// needed) ---
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print!("Starting huge transfer (in-place)...");
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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spi_device_1
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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spi_device_2
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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spi_device_3
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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println!(" SUCCESS");
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delay.delay_ms(250u32);
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}
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}
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