mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-10-02 14:44:42 +00:00
9064177e99
* wip: timg embassy driver - read_raw on timg renamed to now() - timg initialized and stored in static for use in the embassy driver - timg sets alarm value - untested whether alarms actually trigger * TIMG timer driver for esp32, esp32s3 - Adds the timg timer block as a time driver for embassy - Not enabled on the C3 as it only has one timer block, better to use systimer - s2 example added but can't build due to atomic requirements in futures-core * Add S2 atomic support with emulation, fixup embassy support for the S2 * Move executor & static-cell to dev deps. Make eha optional * Add c2 support, run fmt * Update to crates.io embassy releases * Update eha * update timg time driver to new trait * Remove exception feature of esp-backtrace and use the user handler for backtracing * Add async testing workflow * Update systick example * Fix S2 examples * Update xtensa-toolchain * set rustflags for s2 target * Disable systick for esp32s2 until we can fix the noted issues * review improvements - Fix intr prio array being off by one - emabssy time prio interrupt set to max prio - use cfg instead of feature for systick detection * Update example time delays
86 lines
2.3 KiB
Rust
86 lines
2.3 KiB
Rust
//! This shows how to configure UART
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//! You can short the TX and RX pin and see it reads what was written.
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//! Additionally you can connect a logic analzyer to TX and see how the changes
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//! of the configuration change the output signal.
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#![no_std]
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#![no_main]
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use esp32s2_hal::{
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clock::ClockControl,
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gpio::IO,
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pac::Peripherals,
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prelude::*,
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serial::{
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config::{Config, DataBits, Parity, StopBits},
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TxRxPins,
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},
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timer::TimerGroup,
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Delay,
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Rtc,
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Serial,
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};
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use esp_backtrace as _;
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use xtensa_atomic_emulation_trap as _;
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use esp_println::println;
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use nb::block;
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use xtensa_lx_rt::entry;
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut wdt = timer_group0.wdt;
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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// Disable MWDT and RWDT (Watchdog) flash boot protection
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wdt.disable();
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rtc.rwdt.disable();
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let config = Config {
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baudrate: 115200,
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data_bits: DataBits::DataBits8,
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parity: Parity::ParityNone,
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stop_bits: StopBits::STOP1,
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};
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let pins = TxRxPins::new_tx_rx(
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io.pins.gpio1.into_push_pull_output(),
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io.pins.gpio2.into_floating_input(),
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);
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let mut serial1 = Serial::new_with_config(peripherals.UART1, Some(config), Some(pins), &clocks);
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let mut delay = Delay::new(&clocks);
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println!("Start");
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loop {
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serial1.write(0x42).ok();
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let read = block!(serial1.read());
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match read {
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Ok(read) => println!("Read {:02x}", read),
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Err(err) => println!("Error {:?}", err),
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}
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delay.delay_ms(250u32);
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}
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}
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#[xtensa_lx_rt::exception]
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fn exception(cause: xtensa_lx_rt::exception::ExceptionCause, frame: xtensa_lx_rt::exception::Context) {
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use esp_println::*;
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println!("\n\nException occured {:?} {:x?}", cause, frame);
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let backtrace = esp_backtrace::arch::backtrace();
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for b in backtrace.iter() {
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if let Some(addr) = b {
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println!("0x{:x}", addr)
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}
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}
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} |