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https://github.com/esp-rs/esp-hal.git
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db409ffe7b
* Unify the system peripheral Whilst the PCR, SYSTEM and DPORT peripherals are different, we currently use them all in the same way. This PR unifies the peripheral name in the hal to `SYSTEM`. The idea is that they all do the same sort of thing, so we can collect them under the same name, and later down the line we can being to expose differences under an extended API. The benifits to this are imo quite big, the examples now are all identical, which makes things easier for esp-wifi, and paves a path towards the multichip hal. Why not do this in the PAC? Imo the pac should be as close to the hardware as possible, and the HAL is where we should abstractions such as this. * changelog
100 lines
2.4 KiB
Rust
100 lines
2.4 KiB
Rust
//! This shows using Parallel IO to output 4 bit parallel data at 1MHz clock
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//! rate.
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//!
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//! Uses GPIO 1, 2, 3 and 4 as the data pins.
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//! GPIO 5 as the "valid pin" (driven high during an active transfer) and GPIO
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//! 6 as the clock signal output.
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//!
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//! You can use a logic analyzer to see how the pins are used.
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#![no_std]
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#![no_main]
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use esp32c6_hal::{
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clock::ClockControl,
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dma::DmaPriority,
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gdma::Gdma,
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gpio::IO,
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parl_io::{
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BitPackOrder,
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ClkOutPin,
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ParlIoTxOnly,
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SampleEdge,
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TxFourBits,
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TxPinConfigWithValidPin,
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},
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peripherals::Peripherals,
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prelude::*,
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Delay,
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};
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use esp_backtrace as _;
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use esp_println::println;
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let mut tx_descriptors = [0u32; 8 * 3];
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let mut rx_descriptors = [0u32; 8 * 3];
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let dma = Gdma::new(peripherals.DMA);
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let dma_channel = dma.channel0;
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let tx_pins = TxFourBits::new(io.pins.gpio1, io.pins.gpio2, io.pins.gpio3, io.pins.gpio4);
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let pin_conf = TxPinConfigWithValidPin::new(tx_pins, io.pins.gpio5);
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let parl_io = ParlIoTxOnly::new(
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peripherals.PARL_IO,
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dma_channel.configure(
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false,
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&mut tx_descriptors,
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&mut rx_descriptors,
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DmaPriority::Priority0,
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),
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1u32.MHz(),
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&clocks,
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)
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.unwrap();
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let clock_pin = ClkOutPin::new(io.pins.gpio6);
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let mut parl_io_tx = parl_io
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.tx
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.with_config(
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pin_conf,
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clock_pin,
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0,
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SampleEdge::Normal,
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BitPackOrder::Msb,
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)
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.unwrap();
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let mut buffer = dma_buffer();
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for i in 0..buffer.len() {
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buffer[i] = (i % 255) as u8;
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}
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let mut delay = Delay::new(&clocks);
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loop {
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let transfer = parl_io_tx.write_dma(buffer).unwrap();
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// the buffer and driver is moved into the transfer and we can get it back via
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// `wait`
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(buffer, parl_io_tx) = transfer.wait().unwrap();
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println!("Transferred {} bytes", buffer.len());
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delay.delay_ms(500u32);
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}
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}
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fn dma_buffer() -> &'static mut [u8; 4092 * 4] {
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static mut BUFFER: [u8; 4092 * 4] = [0u8; 4092 * 4];
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unsafe { &mut BUFFER }
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}
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