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https://github.com/esp-rs/esp-hal.git
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* RMT: add HIL test that exercises all channels to ensure that there are no issues with channel/register indexing; see also the code comments. no user-facing changes * RMT: store ch_idx instead of channel number `ConstChannelAccess` and `DynChannelAccess` used to store the channel number and have a `Direction` generic parameter. However, there are invalid combinations of `Direction` and the channel number on some chips (e.g. on esp32c3, there is no channel with (Tx, 2), because channel 2 and 3 only support Rx). In constrast, the tuple `(Dir, ch_idx)` also uniquely identifies a channel and its configuration, and any combination of it is valid as long as the channel index is in bounds. This makes it somewhat easier to work with; in particular, it will allow removing bounds checks on ch_idx in a later commit by replacing `ch_idx: u8` with an enum type. This also refactors the `async_interrupt_handler` accordingly. This is user-visible via the `ConstChannelAccess` type, however a later commit in this PR will remove that entirely. * RMT: elide bounds checks via ChannelIndex enum If the channel index is not known at compile time in a given function, the compiler will insert bounds checks on - indexing the STATE global - register access via the PAC The compiler seems to be able to deduplicate them since low-level functions are mostly inlined, but each function will retain at least one bounds check. This change helps the compiler to elide these checks by using a custom type for channel indices that can only take values for which a channel exists. Specifically, this uses an enum to serve as a refinement of u8 to help the compiler restrict value ranges. Due to inlining, this restricted value range is propagated by the compiler until the potential bounds checks, even if there's intermediate cast to u8, cf. https://github.com/rust-lang/rust/issues/109958 There are no user-facing changes. (`ChannelIndex` is `pub` because it appears in a `[doc(hidden)]` trait member.) * RMT: always type-erase channels - remove the `Raw` generic on `Channel`: This simplifies the types, should have negligible performance impact (helped by elided bounds checks via the recently introduced `ChannelIndex` enum), and greatly reduce code size if several channels are used (by avoiding monomorphization per channel) - this also changed the arguments to configure_(tx,rx)_channel such that they don't contain generics, again avoiding code bloat due to monomorphization This requires user code to change type annotations for channels and transactions, and remove any manual type erasure (via `channel.degrade()`). * RMT: impl blocking tx/rx methods directly on Channel There's now only a single type that should implement these methods due to erasing the channel index const generic, so the indirection via a trait serves no purpose. Implementing methods directly on the channel probably also helps to make the docs more discoverable. This requires user code to remove the `TxChannel` and `RxChannel` imports. * RMT: impl async tx/rx methods directly on Channel There's now only a single type that should implement these methods due to erasing the channel index const generic, so the indirection via a trait serves no purpose. Implementing methods directly on the channel probably also helps to make the docs more discoverable. This requires user code to remove the `TxChannelAsync` and `RxChannelAsync` imports. * RMT: impl *ChannelInternal traits only on DynChannelAccess rather than as a blanket impl for RawChannelAccess, which includes ConstChannelAccess: We don't intend to perform any accesses via ConstChannelAccess anymore, so enforce that. We could also get rid of the traits entirely and directly impl their methods for DynChannelAccess, but it seems somewhat useful to keep them around to guarantee that the interfaces in both chip_specific modules are consistent. There are no user-facing changes here. * RMT: remove `pub` on various internal types that used to be visible somewhere in the API's trait bounds, but are not part of the API themselves This is user-visible, but user code should not have used these types in the first place. * RMT: rm ConstChannelAccess, RawChannelAccess, private DynChannelAccess now that Channel has no `Raw: RawChannelAccess` type parameter: - we don't need low-level channel methods to be implemented for ConstChannelAccess, since all accesses go through DynChannelAccess. Thus, remove the *ChannelInternal traits and implement their methods directly on DynChannelAccess - none of these types need to be public (although one might consider actually making them public with an unsafe constructor to provide an unsafe low-level interface to the hardware) This is user-visible (imports need to be removed; they're not used anymore since the previous commit that always type-erased the `Raw` parameter of `Channel`) * RMT: changelog and migration guide for type-erased channels * RMT: (review) remove stray comment * RMT: (review) remove is_tx() from Direction trait we can simply use the const item directly
374 lines
12 KiB
Rust
374 lines
12 KiB
Rust
//! RMT Loopback Test
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//% CHIPS: esp32 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: unstable
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#![no_std]
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#![no_main]
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use esp_hal::{
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Blocking,
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DriverMode,
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gpio::{InputPin, Level, NoPin, OutputPin},
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rmt::{
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Channel,
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Error,
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PulseCode,
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Rmt,
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Rx,
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RxChannelConfig,
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RxChannelCreator,
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Tx,
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TxChannelConfig,
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TxChannelCreator,
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},
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time::Rate,
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};
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use hil_test as _;
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cfg_if::cfg_if! {
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if #[cfg(esp32h2)] {
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const FREQ: Rate = Rate::from_mhz(32);
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const DIV: u8 = 64;
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} else {
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const FREQ: Rate = Rate::from_mhz(80);
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const DIV: u8 = 160;
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}
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}
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fn setup<Dm: DriverMode>(
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rmt: Rmt<'static, Dm>,
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rx: impl InputPin,
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tx: impl OutputPin,
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tx_config: TxChannelConfig,
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rx_config: RxChannelConfig,
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) -> (Channel<Dm, Tx>, Channel<Dm, Rx>) {
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let tx_channel = rmt
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.channel0
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.configure_tx(tx, tx_config.with_clk_divider(DIV))
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.unwrap();
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cfg_if::cfg_if! {
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if #[cfg(any(esp32, esp32s3))] {
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let rx_channel_creator = rmt.channel4;
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} else {
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let rx_channel_creator = rmt.channel2;
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}
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};
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let rx_channel = rx_channel_creator
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.configure_rx(rx, rx_config.with_clk_divider(DIV))
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.unwrap();
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(tx_channel, rx_channel)
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}
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fn generate_tx_data<const TX_LEN: usize>(write_end_marker: bool) -> [PulseCode; TX_LEN] {
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let mut tx_data: [_; TX_LEN] = core::array::from_fn(|i| {
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PulseCode::new(Level::High, (100 + (i * 10) % 200) as u16, Level::Low, 50)
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});
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if write_end_marker {
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tx_data[TX_LEN - 2] = PulseCode::new(Level::High, 3000, Level::Low, 500);
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tx_data[TX_LEN - 1] = PulseCode::end_marker();
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}
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tx_data
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}
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fn do_rmt_loopback_inner<const TX_LEN: usize>(
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tx_channel: Channel<Blocking, Tx>,
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rx_channel: Channel<Blocking, Rx>,
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) {
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let tx_data: [_; TX_LEN] = generate_tx_data(true);
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let mut rcv_data: [PulseCode; TX_LEN] = [PulseCode::default(); TX_LEN];
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let mut rx_transaction = rx_channel.receive(&mut rcv_data).unwrap();
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let mut tx_transaction = tx_channel.transmit(&tx_data).unwrap();
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loop {
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let tx_done = tx_transaction.poll();
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let rx_done = rx_transaction.poll();
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if tx_done && rx_done {
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break;
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}
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}
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tx_transaction.wait().unwrap();
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rx_transaction.wait().unwrap();
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// the last two pulse-codes are the ones which wait for the timeout so
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// they can't be equal
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assert_eq!(&tx_data[..TX_LEN - 2], &rcv_data[..TX_LEN - 2]);
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}
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// Run a test where some data is sent from one channel and looped back to
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// another one for receive, and verify that the data matches.
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fn do_rmt_loopback<const TX_LEN: usize>(tx_memsize: u8, rx_memsize: u8) {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let (rx, tx) = hil_test::common_test_pins!(peripherals);
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let rmt = Rmt::new(peripherals.RMT, FREQ).unwrap();
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let tx_config = TxChannelConfig::default().with_memsize(tx_memsize);
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let rx_config = RxChannelConfig::default()
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.with_idle_threshold(1000)
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.with_memsize(rx_memsize);
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let (tx_channel, rx_channel) = setup(rmt, rx, tx, tx_config, rx_config);
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do_rmt_loopback_inner::<TX_LEN>(tx_channel, rx_channel);
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}
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// Run a test where some data is sent from one channel and looped back to
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// another one for receive, and verify that the data matches.
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async fn do_rmt_loopback_async<const TX_LEN: usize>(tx_memsize: u8, rx_memsize: u8) {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let (rx, tx) = hil_test::common_test_pins!(peripherals);
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let rmt = Rmt::new(peripherals.RMT, FREQ).unwrap().into_async();
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let tx_config = TxChannelConfig::default().with_memsize(tx_memsize);
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let rx_config = RxChannelConfig::default()
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.with_idle_threshold(1000)
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.with_memsize(rx_memsize);
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let (mut tx_channel, mut rx_channel) = setup(rmt, rx, tx, tx_config, rx_config);
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let tx_data: [_; TX_LEN] = generate_tx_data(true);
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let mut rcv_data: [PulseCode; TX_LEN] = [PulseCode::default(); TX_LEN];
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let (rx_res, tx_res) = embassy_futures::join::join(
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rx_channel.receive(&mut rcv_data),
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tx_channel.transmit(&tx_data),
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)
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.await;
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assert!(tx_res.is_ok());
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assert!(rx_res.is_ok());
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// the last two pulse-codes are the ones which wait for the timeout so
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// they can't be equal
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assert_eq!(&tx_data[..TX_LEN - 2], &rcv_data[..TX_LEN - 2]);
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}
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// Run a test that just sends some data, without trying to recive it.
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#[must_use = "Tests should fail on errors"]
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fn do_rmt_single_shot<const TX_LEN: usize>(
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tx_memsize: u8,
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write_end_marker: bool,
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) -> Result<(), Error> {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let (rx, tx) = hil_test::common_test_pins!(peripherals);
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let rmt = Rmt::new(peripherals.RMT, FREQ).unwrap();
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let tx_config = TxChannelConfig::default()
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.with_clk_divider(DIV)
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.with_memsize(tx_memsize);
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let (tx_channel, _) = setup(rmt, rx, tx, tx_config, Default::default());
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let tx_data: [_; TX_LEN] = generate_tx_data(write_end_marker);
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tx_channel.transmit(&tx_data)?.wait().map_err(|(e, _)| e)?;
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Ok(())
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}
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#[cfg(test)]
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#[embedded_test::tests(default_timeout = 1, executor = hil_test::Executor::new())]
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mod tests {
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use super::*;
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#[init]
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fn init() {}
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#[test]
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fn rmt_loopback_simple() {
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// 20 codes fit a single RAM block
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do_rmt_loopback::<20>(1, 1);
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}
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#[test]
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async fn rmt_loopback_simple_async() {
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// 20 codes fit a single RAM block
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do_rmt_loopback_async::<20>(1, 1).await;
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}
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#[test]
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fn rmt_loopback_extended_ram() {
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// 80 codes require two RAM blocks
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do_rmt_loopback::<80>(2, 2);
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}
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// FIXME: This test currently fails on esp32 with an rmt::Error::ReceiverError,
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// which should imply a receiver overrun, which is unexpected (the buffer
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// should hold 2 * 64 codes, which is sufficient).
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// However, the problem already exists exists in the original code that added
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// support for extended channel RAM, so we can't bisect to find a
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// regression. Skip the test for now.
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#[cfg(not(esp32))]
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#[test]
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fn rmt_loopback_tx_wrap() {
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// 80 codes require two RAM blocks; thus a tx channel with only 1 block requires
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// wrapping.
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do_rmt_loopback::<80>(1, 2);
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}
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// FIXME: This test can't work right now, because wrapping rx is not
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// implemented.
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//
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// #[test]
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// fn rmt_loopback_rx_wrap() {
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// // 80 codes require two RAM blocks; thus an rx channel with only 1 block
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// // requires wrapping
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// do_rmt_loopback<80>(2, 1);
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// }
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#[test]
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fn rmt_single_shot_wrap() {
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// Single RAM block (48 or 64 codes), requires wrapping
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do_rmt_single_shot::<80>(1, true).unwrap();
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}
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#[test]
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fn rmt_single_shot_extended() {
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// Two RAM blocks (96 or 128 codes), no wrapping
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do_rmt_single_shot::<80>(2, true).unwrap();
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}
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#[test]
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fn rmt_single_shot_extended_wrap() {
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// Two RAM blocks (96 or 128 codes), requires wrapping
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do_rmt_single_shot::<150>(2, true).unwrap();
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}
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#[test]
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fn rmt_single_shot_fails_without_end_marker() {
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let result = do_rmt_single_shot::<20>(1, false);
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assert!(matches!(result, Err(Error::EndMarkerMissing)));
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}
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#[test]
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fn rmt_overlapping_ram_fails() {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let rmt = Rmt::new(peripherals.RMT, FREQ).unwrap();
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let _ch0 = rmt
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.channel0
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.configure_tx(NoPin, TxChannelConfig::default().with_memsize(2))
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.unwrap();
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// Configuring channel 1 should fail, since channel 0 already uses its memory.
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let ch1 = rmt.channel1.configure_tx(NoPin, TxChannelConfig::default());
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assert!(matches!(ch1, Err(Error::MemoryBlockNotAvailable)));
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}
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#[test]
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fn rmt_overlapping_ram_release() {
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use esp_hal::rmt::TxChannelCreator;
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let rmt = Rmt::new(peripherals.RMT, FREQ).unwrap();
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let ch0 = rmt
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.channel0
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.configure_tx(NoPin, TxChannelConfig::default().with_memsize(2))
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.unwrap();
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// After dropping channel 0, the memory that it reserved should become available
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// again such that channel 1 configuration succeeds.
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core::mem::drop(ch0);
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rmt.channel1
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.configure_tx(NoPin, TxChannelConfig::default())
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.unwrap();
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}
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macro_rules! test_channel_pair {
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(
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$peripherals:ident,
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$tx_pin:ident,
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$rx_pin:ident,
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$tx_channel:ident,
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$rx_channel:ident
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) => {
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// It's currently not possible to reborrow ChannelCreators and reconfigure channels, so
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// we reconfigure the whole peripheral for each sub-test.
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let rmt = Rmt::new($peripherals.RMT.reborrow(), FREQ).unwrap();
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let tx_config = TxChannelConfig::default();
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let rx_config = RxChannelConfig::default().with_idle_threshold(1000);
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let tx_channel = rmt
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.$tx_channel
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.configure_tx($tx_pin.reborrow(), tx_config)
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.unwrap();
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let rx_channel = rmt
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.$rx_channel
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.configure_rx($rx_pin.reborrow(), rx_config)
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.unwrap();
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do_rmt_loopback_inner::<20>(tx_channel, rx_channel);
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};
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}
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// A simple test that uses all channels: This is useful to verify that all channel/register
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// indexing in the driver is correct. The other tests are prone to hide related issues due to
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// using low channel numbers only (in particular 0 for the tx channel).
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#[test]
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fn rmt_use_all_channels() {
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let mut p = esp_hal::init(esp_hal::Config::default());
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let (mut rx, mut tx) = hil_test::common_test_pins!(p);
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// FIXME: Find a way to implement these with less boilerplate and without a macro.
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// Maybe use ChannelCreator::steal() (doesn't help right now because it uses a const
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// generic channel number)?
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// Chips with combined RxTx channels
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#[cfg(esp32)]
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{
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test_channel_pair!(p, tx, rx, channel0, channel1);
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test_channel_pair!(p, tx, rx, channel0, channel2);
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test_channel_pair!(p, tx, rx, channel0, channel3);
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test_channel_pair!(p, tx, rx, channel0, channel4);
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test_channel_pair!(p, tx, rx, channel0, channel5);
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test_channel_pair!(p, tx, rx, channel0, channel6);
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test_channel_pair!(p, tx, rx, channel0, channel7);
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test_channel_pair!(p, tx, rx, channel1, channel0);
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test_channel_pair!(p, tx, rx, channel2, channel0);
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test_channel_pair!(p, tx, rx, channel3, channel0);
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test_channel_pair!(p, tx, rx, channel4, channel0);
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test_channel_pair!(p, tx, rx, channel5, channel0);
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test_channel_pair!(p, tx, rx, channel6, channel0);
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test_channel_pair!(p, tx, rx, channel7, channel0);
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}
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#[cfg(esp32s2)]
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{
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test_channel_pair!(p, tx, rx, channel0, channel1);
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test_channel_pair!(p, tx, rx, channel0, channel2);
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test_channel_pair!(p, tx, rx, channel0, channel3);
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test_channel_pair!(p, tx, rx, channel1, channel0);
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test_channel_pair!(p, tx, rx, channel2, channel0);
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test_channel_pair!(p, tx, rx, channel3, channel0);
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}
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// Chips with separate Rx and Tx channels
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#[cfg(esp32s3)]
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{
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test_channel_pair!(p, tx, rx, channel0, channel4);
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test_channel_pair!(p, tx, rx, channel1, channel5);
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test_channel_pair!(p, tx, rx, channel2, channel6);
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test_channel_pair!(p, tx, rx, channel3, channel7);
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}
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#[cfg(not(any(esp32, esp32s2, esp32s3)))]
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{
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test_channel_pair!(p, tx, rx, channel0, channel2);
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test_channel_pair!(p, tx, rx, channel1, channel3);
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}
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}
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}
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