esp-hal/xtensa-lx-rt/interrupt_level_masks.rs.template

pub enum CpuInterruptLevel {
    Level1,
    Level2,
    Level3,
    Level4,
    Level5,
    Level6,
    Level7,
}

impl CpuInterruptLevel {
    pub fn mask(&self) -> u32 {
        match &self {
            CpuInterruptLevel::Level1 => {{ XCHAL_INTLEVEL1_MASK }}u32,
            CpuInterruptLevel::Level2 => {{ XCHAL_INTLEVEL2_MASK }}u32,
            CpuInterruptLevel::Level3 => {{ XCHAL_INTLEVEL3_MASK }}u32,
            CpuInterruptLevel::Level4 => {{ XCHAL_INTLEVEL4_MASK }}u32,
            CpuInterruptLevel::Level5 => {{ XCHAL_INTLEVEL5_MASK }}u32,
            CpuInterruptLevel::Level6 => {{ XCHAL_INTLEVEL6_MASK }}u32,
            CpuInterruptLevel::Level7 => {{ XCHAL_INTLEVEL7_MASK }}u32,
        }
    }
}