mirror of
https://github.com/esp-rs/esp-hal.git
synced 2025-09-29 13:21:40 +00:00
496 lines
16 KiB
Rust
496 lines
16 KiB
Rust
//! SPI Full Duplex test suite.
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//% CHIPS: esp32 esp32c2 esp32c3 esp32c6 esp32h2 esp32s2 esp32s3
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//% FEATURES: generic-queue
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// FIXME: add async test cases that don't rely on PCNT
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#![no_std]
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#![no_main]
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use embedded_hal::spi::SpiBus;
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#[cfg(pcnt)]
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use embedded_hal_async::spi::SpiBus as SpiBusAsync;
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use esp_hal::{
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dma::{Dma, DmaPriority, DmaRxBuf, DmaTxBuf},
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dma_buffers,
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gpio::{Io, Level, NoPin},
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peripherals::SPI2,
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prelude::*,
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spi::{master::Spi, FullDuplexMode, SpiMode},
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};
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#[cfg(pcnt)]
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use esp_hal::{
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gpio::interconnect::InputSignal,
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pcnt::{channel::EdgeMode, unit::Unit, Pcnt},
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};
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use hil_test as _;
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cfg_if::cfg_if! {
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if #[cfg(any(
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feature = "esp32",
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feature = "esp32s2",
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))] {
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type DmaChannelCreator = esp_hal::dma::Spi2DmaChannelCreator;
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} else {
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type DmaChannelCreator = esp_hal::dma::ChannelCreator<0>;
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}
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}
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struct Context {
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spi: Spi<'static, SPI2, FullDuplexMode>,
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dma_channel: DmaChannelCreator,
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#[cfg(pcnt)]
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pcnt_source: InputSignal,
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#[cfg(pcnt)]
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pcnt_unit: Unit<'static, 0>,
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}
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#[cfg(test)]
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#[embedded_test::tests(executor = esp_hal_embassy::Executor::new())]
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mod tests {
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use defmt::assert_eq;
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use super::*;
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#[init]
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fn init() -> Context {
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let peripherals = esp_hal::init(esp_hal::Config::default());
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let io = Io::new(peripherals.GPIO, peripherals.IO_MUX);
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let sclk = io.pins.gpio0;
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let (_, mosi) = hil_test::common_test_pins!(io);
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let dma = Dma::new(peripherals.DMA);
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cfg_if::cfg_if! {
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if #[cfg(any(feature = "esp32", feature = "esp32s2"))] {
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let dma_channel = dma.spi2channel;
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} else {
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let dma_channel = dma.channel0;
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}
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}
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#[cfg(pcnt)]
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let mosi_loopback_pcnt = mosi.peripheral_input();
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let mosi_loopback = mosi.peripheral_input();
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let spi = Spi::new(peripherals.SPI2, 10000.kHz(), SpiMode::Mode0)
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.with_sck(sclk)
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.with_mosi(mosi)
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.with_miso(mosi_loopback);
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cfg_if::cfg_if! {
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if #[cfg(pcnt)] {
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let pcnt = Pcnt::new(peripherals.PCNT);
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Context {
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spi, dma_channel,
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pcnt_source: mosi_loopback_pcnt,
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pcnt_unit: pcnt.unit0,
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}
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} else {
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Context { spi, dma_channel }
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}
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}
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00u8; 4];
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SpiBus::transfer(&mut ctx.spi, &mut read[..], &write[..])
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.expect("Symmetric transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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#[timeout(3)]
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fn test_asymmetric_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let mut read: [u8; 4] = [0x00; 4];
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SpiBus::transfer(&mut ctx.spi, &mut read[0..2], &write[..])
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.expect("Asymmetric transfer failed");
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assert_eq!(write[0], read[0]);
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assert_eq!(read[2], 0x00u8);
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}
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#[test]
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#[timeout(3)]
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#[cfg(pcnt)]
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fn test_asymmetric_write(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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SpiBus::write(&mut ctx.spi, &write[..]).expect("Asymmetric write failed");
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// Flush because we're not reading, so the write may happen in the background
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ctx.spi.flush().expect("Flush failed");
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assert_eq!(unit.get_value(), 9);
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}
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#[test]
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#[timeout(3)]
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#[cfg(pcnt)]
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fn test_asymmetric_write_transfer(mut ctx: Context) {
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let write = [0xde, 0xad, 0xbe, 0xef];
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let unit = ctx.pcnt_unit;
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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SpiBus::transfer(&mut ctx.spi, &mut [], &write[..]).expect("Asymmetric transfer failed");
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// Flush because we're not reading, so the write may happen in the background
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ctx.spi.flush().expect("Flush failed");
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assert_eq!(unit.get_value(), 9);
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer_huge_buffer(mut ctx: Context) {
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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let mut read = [0x00u8; 4096];
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SpiBus::transfer(&mut ctx.spi, &mut read[..], &write[..]).expect("Huge transfer failed");
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assert_eq!(write, read);
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_transfer_huge_buffer_no_alloc(mut ctx: Context) {
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let mut write = [0x55u8; 4096];
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for byte in 0..write.len() {
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write[byte] = byte as u8;
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}
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ctx.spi
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.transfer_in_place(&mut write[..])
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.expect("Huge transfer failed");
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for byte in 0..write.len() {
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assert_eq!(write[byte], byte as u8);
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}
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}
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#[test]
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#[timeout(3)]
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#[cfg(pcnt)]
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fn test_dma_read_dma_write_pcnt(ctx: Context) {
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const DMA_BUFFER_SIZE: usize = 5;
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
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let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let unit = ctx.pcnt_unit;
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let mut spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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// Fill the buffer where each byte has 3 pos edges.
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dma_tx_buf.as_mut_slice().fill(0b0110_1010);
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for i in 1..4 {
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dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
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let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap();
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(spi, dma_rx_buf) = transfer.wait();
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assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
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let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap();
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(spi, dma_tx_buf) = transfer.wait();
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assert_eq!(unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
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}
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}
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#[test]
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#[timeout(3)]
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#[cfg(pcnt)]
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fn test_dma_read_dma_transfer_pcnt(ctx: Context) {
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const DMA_BUFFER_SIZE: usize = 5;
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
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let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let unit = ctx.pcnt_unit;
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let mut spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
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unit.channel0.set_edge_signal(ctx.pcnt_source);
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unit.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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// Fill the buffer where each byte has 3 pos edges.
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dma_tx_buf.as_mut_slice().fill(0b0110_1010);
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for i in 1..4 {
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dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
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let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap();
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(spi, dma_rx_buf) = transfer.wait();
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assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
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let transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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assert_eq!(unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
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}
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}
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#[test]
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#[cfg(not(esp32))]
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fn test_symmetric_dma_transfer(ctx: Context) {
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// This test case sends a large amount of data, twice, to verify that
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// https://github.com/esp-rs/esp-hal/issues/2151 is and remains fixed.
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(32000);
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let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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for (i, v) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() {
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*v = (i % 255) as u8;
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}
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let mut spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
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for i in 0..4 {
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dma_tx_buf.as_mut_slice()[0] = i as u8;
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*dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8;
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let transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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(spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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assert_eq!(dma_tx_buf.as_slice(), dma_rx_buf.as_slice());
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}
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}
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#[test]
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#[timeout(3)]
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#[cfg(not(feature = "esp32s2"))]
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fn test_asymmetric_dma_transfer(ctx: Context) {
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(2, 4);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
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let spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
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let transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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assert_eq!(dma_tx_buf.as_slice()[0..1], dma_rx_buf.as_slice()[0..1]);
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}
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#[test]
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#[timeout(3)]
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fn test_symmetric_dma_transfer_huge_buffer(ctx: Context) {
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4096);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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for (i, d) in dma_tx_buf.as_mut_slice().iter_mut().enumerate() {
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*d = i as _;
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}
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let spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
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let transfer = spi
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.dma_transfer(dma_rx_buf, dma_tx_buf)
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.map_err(|e| e.0)
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.unwrap();
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let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
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assert_eq!(dma_tx_buf.as_slice(), dma_rx_buf.as_slice());
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}
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#[test]
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#[timeout(3)]
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fn test_dma_bus_symmetric_transfer(ctx: Context) {
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let mut spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0))
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.with_buffers(dma_rx_buf, dma_tx_buf);
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let tx_buf = [0xde, 0xad, 0xbe, 0xef];
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let mut rx_buf = [0; 4];
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spi.transfer(&mut rx_buf, &tx_buf).unwrap();
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assert_eq!(tx_buf, rx_buf);
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}
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#[test]
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#[timeout(3)]
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fn test_dma_bus_asymmetric_transfer(ctx: Context) {
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let mut spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0))
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.with_buffers(dma_rx_buf, dma_tx_buf);
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let tx_buf = [0xde, 0xad, 0xbe, 0xef];
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let mut rx_buf = [0; 4];
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spi.transfer(&mut rx_buf, &tx_buf).unwrap();
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assert_eq!(&tx_buf[0..1], &rx_buf[0..1]);
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}
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#[test]
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#[timeout(3)]
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fn test_dma_bus_symmetric_transfer_huge_buffer(ctx: Context) {
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const DMA_BUFFER_SIZE: usize = 4096;
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(40);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let mut spi = ctx
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.spi
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.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0))
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.with_buffers(dma_rx_buf, dma_tx_buf);
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let tx_buf = core::array::from_fn(|i| i as _);
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let mut rx_buf = [0; DMA_BUFFER_SIZE];
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spi.transfer(&mut rx_buf, &tx_buf).unwrap();
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assert_eq!(tx_buf, rx_buf);
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}
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#[test]
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#[timeout(3)]
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#[cfg(pcnt)]
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async fn test_async_dma_read_dma_write_pcnt(ctx: Context) {
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const DMA_BUFFER_SIZE: usize = 5;
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let mut spi = ctx
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.spi
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.with_dma(
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ctx.dma_channel
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.configure_for_async(false, DmaPriority::Priority0),
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)
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.with_buffers(dma_rx_buf, dma_tx_buf);
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ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
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ctx.pcnt_unit
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.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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let mut receive = [0; DMA_BUFFER_SIZE];
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// Fill the buffer where each byte has 3 pos edges.
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let transmit = [0b0110_1010; DMA_BUFFER_SIZE];
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for i in 1..4 {
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receive.copy_from_slice(&[5, 5, 5, 5, 5]);
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SpiBusAsync::read(&mut spi, &mut receive).await.unwrap();
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assert_eq!(receive, [0, 0, 0, 0, 0]);
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SpiBusAsync::write(&mut spi, &transmit).await.unwrap();
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assert_eq!(ctx.pcnt_unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
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}
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}
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#[test]
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#[timeout(3)]
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#[cfg(pcnt)]
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async fn test_async_dma_read_dma_transfer_pcnt(ctx: Context) {
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const DMA_BUFFER_SIZE: usize = 5;
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let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(DMA_BUFFER_SIZE);
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let dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
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let dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
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let mut spi = ctx
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.spi
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.with_dma(
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ctx.dma_channel
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.configure_for_async(false, DmaPriority::Priority0),
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)
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.with_buffers(dma_rx_buf, dma_tx_buf);
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ctx.pcnt_unit.channel0.set_edge_signal(ctx.pcnt_source);
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ctx.pcnt_unit
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.channel0
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.set_input_mode(EdgeMode::Hold, EdgeMode::Increment);
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let mut receive = [0; DMA_BUFFER_SIZE];
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|
|
|
// Fill the buffer where each byte has 3 pos edges.
|
|
let transmit = [0b0110_1010; DMA_BUFFER_SIZE];
|
|
|
|
for i in 1..4 {
|
|
receive.copy_from_slice(&[5, 5, 5, 5, 5]);
|
|
SpiBusAsync::read(&mut spi, &mut receive).await.unwrap();
|
|
assert_eq!(receive, [0, 0, 0, 0, 0]);
|
|
|
|
SpiBusAsync::transfer(&mut spi, &mut receive, &transmit)
|
|
.await
|
|
.unwrap();
|
|
assert_eq!(ctx.pcnt_unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
|
|
}
|
|
}
|
|
|
|
#[test]
|
|
#[timeout(3)]
|
|
fn test_write_read(ctx: Context) {
|
|
let spi = ctx
|
|
.spi
|
|
.with_mosi(NoPin)
|
|
.with_miso(Level::High)
|
|
.with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
|
|
|
|
let (rx_buffer, rx_descriptors, tx_buffer, tx_descriptors) = dma_buffers!(4);
|
|
let mut dma_rx_buf = DmaRxBuf::new(rx_descriptors, rx_buffer).unwrap();
|
|
let mut dma_tx_buf = DmaTxBuf::new(tx_descriptors, tx_buffer).unwrap();
|
|
|
|
dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
|
|
|
|
let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap();
|
|
let (spi, dma_tx_buf) = transfer.wait();
|
|
|
|
dma_rx_buf.as_mut_slice().fill(0);
|
|
let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap();
|
|
let (spi, mut dma_rx_buf) = transfer.wait();
|
|
|
|
let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap();
|
|
let (spi, _dma_tx_buf) = transfer.wait();
|
|
|
|
dma_rx_buf.as_mut_slice().fill(0);
|
|
let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap();
|
|
let (_, dma_rx_buf) = transfer.wait();
|
|
|
|
assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
|
|
}
|
|
}
|