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https://github.com/esp-rs/esp-hal.git
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9a5a546228
* esp32 & esp32s2 sharing scripts * add wokwi files * Add fixup section for esp32s2, fix ordering of sectino includes * Remove debug asm file * Use shared linker scripts for s3 with fixups * Add external.x sections back * Move ld scripts into esp-hal-common * esp32c3 unified linker scripts - rework original c3 script to use the xtensa named sections (e.g, _SECTIONNAME_start) - Add fixups in esp32c3 specific linker - Remove useless text section start and end (not required when using any form of bootloader) * Add RTC alias'. Move some shared fixups to a file * comment and cleanup * unify c2 linker script * unify c6 linker script * remove debug configs * use new esp-riscv-rt * fmt * align db symbol names * fix s3 db
38 lines
1.2 KiB
Plaintext
38 lines
1.2 KiB
Plaintext
MEMORY
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{
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/* MEMORY_MAP = [
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[0x00000000, 0x00010000, "PADDING"],
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[0x42800000, 0x43000000, "DROM"],
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[0x40800000, 0x40880000, "RAM"],
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[0x40800000, 0x40880000, "BYTE_ACCESSIBLE"],
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[0x4004AC00, 0x40050000, "DROM_MASK"],
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[0x40000000, 0x4004AC00, "ROM_MASK"],
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[0x42000000, 0x42800000, "ROM"],
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[0x40800000, 0x40880000, "RAM"],
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[0x50000000, 0x50004000, "RTC_RAM"],
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[0x50000000, 0x50004000, "RTC_RAM"],
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[0x600FE000, 0x60100000, "MEM_INTERNAL2"],
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] */
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/* 512K of on soc RAM, 32K reserved for cache */
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ICACHE : ORIGIN = 0x40800000, LENGTH = 32K
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/* Instruction and Data RAM */
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RAM : ORIGIN = 0x40800000 + 32K, LENGTH = 512K - 32K
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/* External flash */
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/* Instruction and Data ROM */
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ROM : ORIGIN = 0x42000000 + 0x20, LENGTH = 0x400000 - 0x20
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/* RTC fast memory (executable). Persists over deep sleep. */
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RTC_FAST : ORIGIN = 0x50000000, LENGTH = 16K /*- ESP_BOOTLOADER_RESERVE_RTC*/
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}
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REGION_ALIAS("ROTEXT", ROM);
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REGION_ALIAS("RODATA", ROM);
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REGION_ALIAS("RWTEXT", RAM);
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REGION_ALIAS("RWDATA", RAM);
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REGION_ALIAS("RTC_FAST_RWTEXT", RTC_FAST);
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REGION_ALIAS("RTC_FAST_RWDATA", RTC_FAST);
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