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https://github.com/esp-rs/esp-hal.git
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91ea205446
* esp32: Fix typo in Frequency word in some identifiers Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com> * esp32c3: Add support for PLL clock configuration Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com> * clock: Move definition of Clock types to common level Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com> * esp32c3: Add support for RTC Clock configuration Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com> * esp32c3: Add example for the RTC Watchdog Timer driver Signed-off-by: Gustavo Henrique Nihei <gustavo.nihei@espressif.com>
91 lines
2.5 KiB
Rust
91 lines
2.5 KiB
Rust
//! This shows how to use the TIMG peripheral interrupts.
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//! There is TIMG0 and TIMG1 each of them containing a general purpose timer and
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//! a watchdog timer.
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#![no_std]
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#![no_main]
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use core::cell::RefCell;
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use bare_metal::Mutex;
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use esp32c3_hal::{
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clock::ClockControl,
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interrupt,
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pac::{self, Peripherals, TIMG0, TIMG1},
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prelude::*,
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timer::{Timer, Timer0, TimerGroup},
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Rtc,
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};
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use panic_halt as _;
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use riscv_rt::entry;
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static mut TIMER0: Mutex<RefCell<Option<Timer<Timer0<TIMG0>>>>> = Mutex::new(RefCell::new(None));
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static mut TIMER1: Mutex<RefCell<Option<Timer<Timer0<TIMG1>>>>> = Mutex::new(RefCell::new(None));
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take().unwrap();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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// Disable the watchdog timers. For the ESP32-C3, this includes the Super WDT,
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// the RTC WDT, and the TIMG WDTs.
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let mut rtc = Rtc::new(peripherals.RTC_CNTL);
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let timer_group0 = TimerGroup::new(peripherals.TIMG0, &clocks);
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let mut timer0 = timer_group0.timer0;
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let mut wdt0 = timer_group0.wdt;
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let timer_group1 = TimerGroup::new(peripherals.TIMG1, &clocks);
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let mut timer1 = timer_group1.timer0;
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let mut wdt1 = timer_group1.wdt;
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rtc.swd.disable();
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rtc.rwdt.disable();
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wdt0.disable();
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wdt1.disable();
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interrupt::enable(pac::Interrupt::TG0_T0_LEVEL, interrupt::Priority::Priority1).unwrap();
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timer0.start(500u64.millis());
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timer0.listen();
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interrupt::enable(pac::Interrupt::TG1_T0_LEVEL, interrupt::Priority::Priority1).unwrap();
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timer1.start(1u64.secs());
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timer1.listen();
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riscv::interrupt::free(|_cs| unsafe {
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TIMER0.get_mut().replace(Some(timer0));
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TIMER1.get_mut().replace(Some(timer1));
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});
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unsafe {
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riscv::interrupt::enable();
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}
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loop {}
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}
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#[interrupt]
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fn TG0_T0_LEVEL() {
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riscv::interrupt::free(|cs| unsafe {
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esp_println::println!("Interrupt 1");
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let mut timer0 = TIMER0.borrow(*cs).borrow_mut();
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let timer0 = timer0.as_mut().unwrap();
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timer0.clear_interrupt();
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timer0.start(500u64.millis());
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});
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}
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#[interrupt]
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fn TG1_T0_LEVEL() {
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riscv::interrupt::free(|cs| unsafe {
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esp_println::println!("Interrupt 11");
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let mut timer1 = TIMER1.borrow(*cs).borrow_mut();
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let timer1 = timer1.as_mut().unwrap();
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timer1.clear_interrupt();
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timer1.start(1u64.secs());
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});
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}
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