9e190f112d
* Use riscv-rt's startup code * CHANGELOG.md * Enable v-trap - get rid of one unused function * Re-use riscv-rt's TrapFrame instead of keeping a copy of it * fmt * Update riscv-rt rev * Enable defmt * use riscv-rt's trap handling * Compile on stable * (Re)add the SP fixing code * Move comment * Update `riscv*` deps * esp-riscv-rt: Remove the (unused) CI feature
esp-lp-hal
Bare-metal (no_std) hardware abstraction layer for the low-power RISC-V coprocessors found in the ESP32-C6, ESP32-S2, and ESP32-S3 from Espressif.
Implements a number of blocking and, where applicable, async traits from the various packages in the embedded-hal repository.
For help getting started with this HAL, please refer to The Rust on ESP Book and the [documentation].
Documentation
Supported Devices
| Chip | Datasheet | Technical Reference Manual | Target |
|---|---|---|---|
| ESP32-C6 | ESP32-C6 | ESP32-C6 | riscv32imac-unknown-none-elf |
| ESP32-S2 | ESP32-S2 | ESP32-S2 | riscv32imc-unknown-none-elf |
| ESP32-S3 | ESP32-S3 | ESP32-S3 | riscv32imc-unknown-none-elf |
Minimum Supported Rust Version (MSRV)
This crate is guaranteed to compile when using the latest stable Rust version at the time of the crate's release. It might compile with older versions, but that may change in any new release, including patches.
License
Licensed under either of:
- Apache License, Version 2.0 (LICENSE-APACHE or http://www.apache.org/licenses/LICENSE-2.0)
- MIT license (LICENSE-MIT or http://opensource.org/licenses/MIT)
at your option.
Contribution
Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.