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https://github.com/esp-rs/esp-hal.git
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db409ffe7b
* Unify the system peripheral Whilst the PCR, SYSTEM and DPORT peripherals are different, we currently use them all in the same way. This PR unifies the peripheral name in the hal to `SYSTEM`. The idea is that they all do the same sort of thing, so we can collect them under the same name, and later down the line we can being to expose differences under an extended API. The benifits to this are imo quite big, the examples now are all identical, which makes things easier for esp-wifi, and paves a path towards the multichip hal. Why not do this in the PAC? Imo the pac should be as close to the hardware as possible, and the HAL is where we should abstractions such as this. * changelog
92 lines
2.3 KiB
Rust
92 lines
2.3 KiB
Rust
//! Demonstrates decoding pulse sequences with RMT
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//! Connect GPIO15 to GPIO4
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#![no_std]
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#![no_main]
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use esp32_hal::{
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clock::ClockControl,
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gpio::IO,
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peripherals::Peripherals,
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prelude::*,
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rmt::{PulseCode, RxChannel, RxChannelConfig, RxChannelCreator},
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Delay,
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Rmt,
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};
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use esp_backtrace as _;
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use esp_println::println;
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#[entry]
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fn main() -> ! {
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let peripherals = Peripherals::take();
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let system = peripherals.SYSTEM.split();
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let clocks = ClockControl::boot_defaults(system.clock_control).freeze();
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let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
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let mut out = io.pins.gpio15.into_push_pull_output();
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let rmt = Rmt::new(peripherals.RMT, 80u32.MHz(), &clocks).unwrap();
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let mut channel = rmt
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.channel0
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.configure(
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io.pins.gpio4,
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RxChannelConfig {
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clk_divider: 1,
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idle_threshold: 0b111_1111_1111_1111,
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..RxChannelConfig::default()
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},
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)
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.unwrap();
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let mut delay = Delay::new(&clocks);
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let mut data = [PulseCode {
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level1: true,
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length1: 1,
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level2: false,
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length2: 1,
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}; 48];
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loop {
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for x in data.iter_mut() {
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x.length1 = 0;
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x.length2 = 0;
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}
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let transaction = channel.receive(&mut data).unwrap();
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// simulate input
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for i in 0u32..5u32 {
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out.set_high().unwrap();
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delay.delay_us(i * 10 + 20);
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out.set_low().unwrap();
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delay.delay_us(i * 20 + 20);
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}
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match transaction.wait() {
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Ok(channel_res) => {
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channel = channel_res;
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for entry in &data[..data.len()] {
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if entry.length1 == 0 {
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break;
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}
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println!("{} {}", entry.level1, entry.length1);
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if entry.length2 == 0 {
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break;
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}
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println!("{} {}", entry.level2, entry.length2);
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}
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println!();
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}
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Err((_err, channel_res)) => {
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channel = channel_res;
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println!("Error");
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}
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}
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delay.delay_ms(1500u32);
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}
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}
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