esp-hal/esp-riscv-rt
Björn Quentin c1912fc079
C6/H2: flip-link feature (#1008)
* C6/H2: flip-link feature

* CHANGELOG.md entry

* Include .wifiextrairam in .rwtext.wifi

* Set exception code 14 if SP was out of bounds
2023-12-11 12:45:07 +00:00
..
2023-12-11 12:45:07 +00:00
2023-12-11 12:45:07 +00:00

esp-riscv-rt

Crates.io docs.rs MSRV Crates.io

Minimal runtime / startup for RISC-V CPUs from Espressif.

Much of the code in this repository originated in the rust-embedded/riscv-rt repository.

Documentation

Minimum Supported Rust Version (MSRV)

This crate is guaranteed to compile on stable Rust 1.60 and up. It might compile with older versions but that may change in any new patch release.

License

Licensed under either of:

at your option.

Contribution

Unless you explicitly state otherwise, any contribution intentionally submitted for inclusion in the work by you, as defined in the Apache-2.0 license, shall be dual licensed as above, without any additional terms or conditions.