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https://github.com/esp-rs/esp-hal.git
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c612fecfae
* Clear LP_RAM/RTC RAM to make sure .bss is cleared * Rename `ulp-riscv-hal` to `esp-ulp-riscv-hal` * CHANGELOG.md entry
98 lines
2.0 KiB
Rust
98 lines
2.0 KiB
Rust
#![no_std]
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use core::arch::global_asm;
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pub mod delay;
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pub mod gpio;
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pub mod prelude;
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#[cfg(feature = "esp32s2")]
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use esp32s2_ulp as pac;
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#[cfg(feature = "esp32s3")]
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use esp32s3_ulp as pac;
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global_asm!(
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r#"
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.section .text.vectors
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.global irq_vector
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.global reset_vector
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/* The reset vector, jumps to startup code */
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reset_vector:
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j __start
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/* Interrupt handler */
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.balign 16
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irq_vector:
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ret
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.section .text
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__start:
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/* setup the stack pointer */
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la sp, __stack_top
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call ulp_riscv_rescue_from_monitor
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call rust_main
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call ulp_riscv_halt
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loop:
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j loop
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"#
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);
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#[link_section = ".init.rust"]
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#[export_name = "rust_main"]
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unsafe extern "C" fn lp_core_startup() -> ! {
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extern "Rust" {
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fn main() -> !;
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}
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main();
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}
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#[link_section = ".init.rust"]
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#[export_name = "ulp_riscv_rescue_from_monitor"]
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unsafe extern "C" fn ulp_riscv_rescue_from_monitor() {
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// Rescue RISCV from monitor state.
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let rtc_cntl = unsafe { pac::RTC_CNTL::steal() };
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// TODO align naming in PACs
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#[cfg(feature = "esp32s2")]
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rtc_cntl
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.cocpu_ctrl
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.modify(|_, w| w.cocpu_done().clear_bit().cocpu_shut_reset_en().clear_bit());
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#[cfg(feature = "esp32s3")]
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rtc_cntl
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.rtc_cocpu_ctrl
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.modify(|_, w| w.cocpu_done().clear_bit().cocpu_shut_reset_en().clear_bit());
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}
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#[link_section = ".init.rust"]
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#[export_name = "ulp_riscv_halt"]
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unsafe extern "C" fn ulp_riscv_halt() {
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let rtc_cntl = unsafe { pac::RTC_CNTL::steal() };
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// TODO align naming in PACs
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#[cfg(feature = "esp32s2")]
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{
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rtc_cntl
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.cocpu_ctrl
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.modify(|_, w| w.cocpu_shut_2_clk_dis().variant(0x3f));
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rtc_cntl.cocpu_ctrl.modify(|_, w| w.cocpu_done().set_bit());
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}
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#[cfg(feature = "esp32s3")]
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{
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rtc_cntl
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.rtc_cocpu_ctrl
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.modify(|_, w| w.cocpu_shut_2_clk_dis().variant(0x3f));
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rtc_cntl
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.rtc_cocpu_ctrl
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.modify(|_, w| w.cocpu_done().set_bit());
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}
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#[allow(clippy::empty_loop)]
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loop {}
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}
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